Alejandro Valero

@inproceedings{valero2011improving,

title = {Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour},

author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Pedro Lopez and Jose Duato},

url = {https://ieeexplore.ieee.org/document/6113824},

doi = {https://doi.org/10.1109/PACT.2011.47},

isbn = {978-1-4577-1794-9},

year  = {2011},

date = {2011-10-10},

urldate = {2011-01-01},

booktitle = {Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT 2011)},

pages = {214-214},

organization = {IEEE},

abstract = {Last-Level Caches (LLCs) implement the LRU algorithm to exploit temporal locality, but its performance is quite far of Belady's optimal algorithm as the number of ways increases. One of the main reasons because of LRU does not reach good performance in LLCs is that this policy forces a block to descend until the bottom of the stack before eviction. Nevertheless, most of the blocks that leave the MRU position are not referenced again before eviction. This work pursues to select candidate blocks to be victimized before reaching the bottom of the stack. To this end, this work defines the number of MRU-Tours (MRUTs) of a block as the number of times that a block enters in the MRU position during its live time. Based on the fact that most of the blocks exhibit a single MRUT, this work presents the family of MRUT-based algorithms aimed at exploiting this block behavior to improve performance.},

keywords = {},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{valero2009hybrid,

title = {An hybrid eDRAM/SRAM macrocell to implement first-level data caches},

author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Vicente Lorente and Ramon Canal and Pedro López and José Duato},

url = {https://ieeexplore.ieee.org/document/5375366},

doi = {https://doi.org/10.1145/1669112.1669140},

isbn = {978-1-60558-798-1},

year  = {2009},

date = {2009-12-16},

urldate = {2009-01-01},

booktitle = {Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2009)},

pages = {213-221},

organization = {ACM},

abstract = {SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology, thus overcoming the speed limit of typical DRAM cells. In this paper we propose an n-bit macrocell that implements one static cell, and n-1 dynamic cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Our study shows that in a four-way set-associative cache with this macrocell compared to an SRAM based with the same capacity, leakage is reduced by about 75% and area more than half with a minimal impact on performance. Architectural mechanisms have also been devised to avoid refresh logic. Experimental results show that no performance is lost when the retention time is larger than 50 K processor cycles. In addition, the proposed delayed writeback policy that avoids refreshing performs a similar amount of writebacks than a conventional cache with the same organization, so no power wasting is incurred.},

keywords = {},

pubstate = {published},

tppubtype = {inproceedings}

}