Alejandro Valero

Alejandro Valero received the BS, MS, and PhD degrees in Computer Engineering from the Universitat Politècnica de València, Spain, in 2009, 2011, and 2013, respectively. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston (MA), USA, and the University of Cambridge, UK. From 2016 to 2021 he was an Assistant Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain. Since 2021 he is an Associate Professor with the same department and institution. Prof. Valero has taught several courses on computer organization, including digital design, computer organization and design, heterogeneous systems programming and design, data center design, and operating systems. His PhD research contributions to the design of high-performance, energy-efficient CPU memory subsystems were recognized by multiple entities. He received the Intel Doctoral Student Honor Program Award in 2012 and the Gold Medal in the ACM Student Research Competition (SRC) held in the 27th International Conference on Supercomputing (ICS 2013). His research interests mainly focus on the design of memory hierarchies in terms of performance, energy efficiency, and reliability for different microprocessors: CPU systems, general-purpose GPUs, and accelerators for computer vision algorithms. Prof. Valero has participated in more than 20 national and local funded research projects and has published more than 30 papers in the main venues of the computer architecture area, such as the IEEE/ACM International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), IEEE Transactions on Computers, and IEEE Transactions on Very Large Scale Integration (VLSI) Systems. He has served as Technical Program Committee member in a significant number of conferences, workshops, and research competitions, like the Design Automation and Test in Europe (DATE) conference, the IEEE International Conference on Computer Design (ICCD), the Performance Modeling, Benchmarking, and Simulation of High Performance Computer Systems (PMBS) workshop, and the ACM SRC Grand Finals. He is also a frequent reviewer in top journals of his area, such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Dependable and Secure Computing, and ACM Transactions on Design Automation of Electronic Systems. He was a recipient of the Outstanding Reviewer Award in the Design Methods and Tools track at the DATE 2024 conference. Prof. Valero is a member of the ACM, the Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), the Aragon Institute of Engineering Research (I3A), and an affiliated member of the High Performance, Edge, And Cloud Computing (HiPEAC) European Network of Excellence.