Alejandro Valero

@article{candel2019efficient,

title = {Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance},

author = {Francisco Candel and Alejandro Valero and Salvador Petit and Julio Sahuquillo},

url = {https://ieeexplore.ieee.org/document/8681093},

doi = {https://doi.org/10.1109/TC.2019.2907591},

issn = {0018-9340},

year  = {2019},

date = {2019-10-01},

urldate = {2019-01-01},

journal = {IEEE Transactions on Computers},

volume = {68},

number = {10},

pages = {1442-1454},

publisher = {IEEE},

abstract = {To support the massive amount of memory accesses that GPGPU applications generate, GPU memory hierarchies are becoming more and more complex, and the Last Level Cache (LLC) size considerably increases each GPU generation. This paper shows that counter-intuitively, enlarging the LLC brings marginal performance gains in most applications. In other words, increasing the LLC size does not scale neither in performance nor energy consumption. We examine how LLC misses are managed in typical GPUs, and we find that in most cases the way LLC misses are managed are precisely the main performance limiter. This paper proposes a novel approach that addresses this shortcoming by leveraging a tiny additional Fetch and Replacement Cache-like structure (FRC) that stores control and coherence information of the incoming blocks until they are fetched from main memory. Then, the fetched blocks are swapped with the victim blocks (i.e., selected to be replaced) in the LLC, and the eviction of such victim blocks is performed from the FRC. This approach improves performance due to three main reasons: i) the lifetime of blocks being replaced is enlarged, ii) the main memory path is unclogged on long bursts of LLC misses, and iii) the average LLC miss latency is reduced. The proposal improves the LLC hit ratio, memory-level parallelism, and reduces the miss latency compared to much larger conventional caches. Moreover, this is achieved with reduced energy consumption and with much less area requirements. Experimental results show that the proposed FRC cache scales in performance with the number of GPU compute units and the LLC size, since, depending on the FRC size, performance improves ranging from 30 to 67 percent for a modern baseline GPU card, and from 32 to 118 percent for a larger GPU. In addition, energy consumption is reduced on average from 49 to 57 percent for the larger GPU. These benefits come with a small area increase (by 7.3 percent) over the LLC baseline.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Valero2019,

title = {An Aging-Aware GPU Register File Design Based on Data Redundancy},

author = {Alejandro Valero and Francisco Candel and Darío Suárez Gracia and Salvador Petit and Julio Sahuquillo},

url = {https://ieeexplore.ieee.org/document/8395355},

doi = {https://doi.org/10.1109/TC.2018.2849376},

issn = {0018-9340},

year  = {2019},

date = {2019-01-01},

urldate = {2019-01-01},

journal = {IEEE Transactions on Computers},

volume = {68},

issue = {1},

pages = {4-20},

abstract = {Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage Vth over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall Vth degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100 percent ‘0’ and ‘1’ duty cycle distributions). On average, the proposal reduces these distributions by 58 and 68 percent, respectively, which translates into Vth degradation savings by 54 and 62 percent, respectively.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}