2022
Artículos de revista
Alcolea, Adrián; Resano, Javier
Bayesian Neural Networks to Analyze Hyperspectral Datasets Using Uncertainty Metrics Artículo de revista
En: IEEE Transactions on Geoscience and Remote Sensing, vol. 60, pp. 1-10, 2022, ISSN: 1558-0644.
@article{9881579,
title = {Bayesian Neural Networks to Analyze Hyperspectral Datasets Using Uncertainty Metrics},
author = {Adrián Alcolea and Javier Resano},
doi = {10.1109/TGRS.2022.3205119},
issn = {1558-0644},
year = {2022},
date = {2022-01-01},
journal = {IEEE Transactions on Geoscience and Remote Sensing},
volume = {60},
pages = {1-10},
abstract = {Machine learning techniques, and specifically neural networks, have proved to be very useful tools for image classification tasks. Nevertheless, measuring the reliability of these networks and calibrating them accurately are very complex. This is even more complex in a field like hyperspectral imaging, where labeled data are scarce and difficult to generate. Bayesian neural networks (BNNs) allow to obtain uncertainty metrics related to the data processed (aleatoric), and to the uncertainty generated by the model selected (epistemic). On this work, we will demonstrate the utility of BNNs by analyzing the uncertainty metrics obtained by a BNN over five of the most used hyperspectral images datasets. In addition, we will illustrate how these metrics can be used for several practical applications such as identifying predictions that do not reach the required level of accuracy, detecting mislabeling in the dataset, or identifying when the predictions are affected by the increase of the level of noise in the input data.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Machine learning techniques, and specifically neural networks, have proved to be very useful tools for image classification tasks. Nevertheless, measuring the reliability of these networks and calibrating them accurately are very complex. This is even more complex in a field like hyperspectral imaging, where labeled data are scarce and difficult to generate. Bayesian neural networks (BNNs) allow to obtain uncertainty metrics related to the data processed (aleatoric), and to the uncertainty generated by the model selected (epistemic). On this work, we will demonstrate the utility of BNNs by analyzing the uncertainty metrics obtained by a BNN over five of the most used hyperspectral images datasets. In addition, we will illustrate how these metrics can be used for several practical applications such as identifying predictions that do not reach the required level of accuracy, detecting mislabeling in the dataset, or identifying when the predictions are affected by the increase of the level of noise in the input data.
Aramendía, Maite; García-Mesa, Juan Carlos; Alonso, Elisa Vereda; Garde, Raúl; Bazo, Antonio; Resano, Javier; Resano, Martín
A novel approach for adapting the standard addition method to single particle-ICP-MS for the accurate determination of NP size and number concentration in complex matrices Artículo de revista
En: Analytica Chimica Acta, vol. 1205, pp. 339738, 2022, ISSN: 0003-2670.
@article{ARAMENDIA2022339738,
title = {A novel approach for adapting the standard addition method to single particle-ICP-MS for the accurate determination of NP size and number concentration in complex matrices},
author = {Maite Aramendía and Juan Carlos García-Mesa and Elisa Vereda Alonso and Raúl Garde and Antonio Bazo and Javier Resano and Martín Resano},
url = {https://www.sciencedirect.com/science/article/pii/S0003267022003099},
doi = {https://doi.org/10.1016/j.aca.2022.339738},
issn = {0003-2670},
year = {2022},
date = {2022-01-01},
journal = {Analytica Chimica Acta},
volume = {1205},
pages = {339738},
abstract = {This paper presents a novel approach, based on the standard addition method, for overcoming the matrix effects that often hamper the accurate characterization of nanoparticles (NPs) in complex samples via single particle inductively coupled plasma mass spectrometry (SP-ICP-MS). In this approach, calibration of the particle size is performed by two different methods: (i) by spiking a suspension of NPs standards of known size containing the analyte, or (ii) by spiking the sample with ionic standards; either way, the measured sensitivity is used in combination with the transport efficiency (TE) for sizing the NPs. Moreover, such transport efficiency can be readily obtained from the data obtained via both calibration methods mentioned above, so that the particle number concentration can also be determined. The addition of both ionic and NP standards can be performed on-line, by using a T-piece with two inlet lines of different dimensions. The smaller of the two is used for the standards, thus ensuring a constant and minimal sample dilution. As a result of the spiking of the samples, mixed histograms including the signal of the sample and that of the standards are obtained. However, the use of signal deconvolution approaches permits to extract the information, even in cases of signal populations overlapping. For proofing the concept, characterization of a 50 nm AuNPs suspension prepared in three different media (i.e., deionized water, 5% ethanol, and 2.5% tetramethyl ammonium hydroxide-TMAH) was carried out. Accurate results were obtained in all cases, in spite of the matrix effects detected in some media. Overall, the approach proposed offers flexibility, so it can be adapted to different situations, but it might be specially indicated for samples for which the matrix is not fully known and/or dilution is not possible/recommended.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
This paper presents a novel approach, based on the standard addition method, for overcoming the matrix effects that often hamper the accurate characterization of nanoparticles (NPs) in complex samples via single particle inductively coupled plasma mass spectrometry (SP-ICP-MS). In this approach, calibration of the particle size is performed by two different methods: (i) by spiking a suspension of NPs standards of known size containing the analyte, or (ii) by spiking the sample with ionic standards; either way, the measured sensitivity is used in combination with the transport efficiency (TE) for sizing the NPs. Moreover, such transport efficiency can be readily obtained from the data obtained via both calibration methods mentioned above, so that the particle number concentration can also be determined. The addition of both ionic and NP standards can be performed on-line, by using a T-piece with two inlet lines of different dimensions. The smaller of the two is used for the standards, thus ensuring a constant and minimal sample dilution. As a result of the spiking of the samples, mixed histograms including the signal of the sample and that of the standards are obtained. However, the use of signal deconvolution approaches permits to extract the information, even in cases of signal populations overlapping. For proofing the concept, characterization of a 50 nm AuNPs suspension prepared in three different media (i.e., deionized water, 5% ethanol, and 2.5% tetramethyl ammonium hydroxide-TMAH) was carried out. Accurate results were obtained in all cases, in spite of the matrix effects detected in some media. Overall, the approach proposed offers flexibility, so it can be adapted to different situations, but it might be specially indicated for samples for which the matrix is not fully known and/or dilution is not possible/recommended.
Book Sections
Escuin, Carlos; Khan, Asif Ali; Ibañez, Pablo; Monreal, Teresa; Viñals, Victor; Castrillon, Jeronimo
Hycsim: A rapid design space exploration tool for emerging hybrid last-level caches Book Section
En: System Engineering for constrained embedded systems, pp. 53–58, 2022.
@incollection{escuin2022hycsim,
title = {Hycsim: A rapid design space exploration tool for emerging hybrid last-level caches},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibañez and Teresa Monreal and Victor Viñals and Jeronimo Castrillon},
year = {2022},
date = {2022-01-01},
booktitle = {System Engineering for constrained embedded systems},
pages = {53–58},
keywords = {},
pubstate = {published},
tppubtype = {incollection}
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Proceedings Articles
Gracia, Darío Suárez; Valero, Alejandro; Tejero, Rubén Gran; Villarroya-Gaudó, María; Viñals, Víctor
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter Proceedings Article
En: Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022), pp. 1-6, 2022, ISBN: 978-1-6654-5950-1.
@inproceedings{Gracia2022,
title = {peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter},
author = {Darío Suárez Gracia and Alejandro Valero and Rubén Gran Tejero and María Villarroya-Gaudó and Víctor Viñals},
url = {https://ieeexplore.ieee.org/document/9970050},
doi = {https://doi.org/10.1109/DCIS55711.2022.9970050},
isbn = {978-1-6654-5950-1},
year = {2022},
date = {2022-11-16},
urldate = {2022-11-16},
booktitle = {Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022)},
pages = {1-6},
abstract = {The fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience.
Tárrega, Hugo; Valero, Alejandro; Lorente, Vicente; Petit, Salvador; Sahuquillo, Julio
Fast-Track Cache: a huge racetrack memory L1 data cache Proceedings Article
En: Proceedings of the 36th ACM International Conference on Supercomputing (ICS 2022), pp. 1-12, ACM, 2022, ISBN: 978-1-4503-9281-5.
@inproceedings{Tárrega2022,
title = {Fast-Track Cache: a huge racetrack memory L1 data cache},
author = {Hugo Tárrega and Alejandro Valero and Vicente Lorente and Salvador Petit and Julio Sahuquillo},
url = {https://dl.acm.org/doi/10.1145/3524059.3532383},
doi = {https://doi.org/10.1145/3524059.3532383},
isbn = {978-1-4503-9281-5},
year = {2022},
date = {2022-06-28},
urldate = {2022-06-28},
booktitle = {Proceedings of the 36th ACM International Conference on Supercomputing (ICS 2022)},
pages = {1-12},
publisher = {ACM},
abstract = {First-level (L1) caches have been traditionally implemented with Static Random-Access Memory (SRAM) technology, since it is the fastest memory technology, and L1 caches call for tight timing constraints in the processor pipeline. However, one of the main downsides of SRAM is its low density, which prevents L1 caches to improve their storage capacity beyond a few tens of KB. On the other hand, the recent Domain Wall Memory (DWM) technology overcomes such a constraint by arranging multiple bits in a magnetic racetrack, and sharing a header to access those bits. Accessing a bit requires a shift operation to align the target bit under the header. Such shifts increase the final access latency, which is the main reason why DWM has been mostly used to implement slow last-level caches. This paper proposes a novel DWM-based L1 cache data array design, namely Fast-Track Cache (FTC), that allows L1 caches with bigger storage capacities while reducing the shift overhead thanks to an enhanced exploitation of spatial and temporal localities. Experimental results show that most FTC accesses do not require shifts. As a consequence, and due to its larger capacity, FTC improves the processor performance on average by 15% over a conventional SRAM memory subsystem and the state-of-the-art TapeCache architecture based on DWM. At the same time, energy savings are improved on average by 34% over the conventional design.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
First-level (L1) caches have been traditionally implemented with Static Random-Access Memory (SRAM) technology, since it is the fastest memory technology, and L1 caches call for tight timing constraints in the processor pipeline. However, one of the main downsides of SRAM is its low density, which prevents L1 caches to improve their storage capacity beyond a few tens of KB. On the other hand, the recent Domain Wall Memory (DWM) technology overcomes such a constraint by arranging multiple bits in a magnetic racetrack, and sharing a header to access those bits. Accessing a bit requires a shift operation to align the target bit under the header. Such shifts increase the final access latency, which is the main reason why DWM has been mostly used to implement slow last-level caches. This paper proposes a novel DWM-based L1 cache data array design, namely Fast-Track Cache (FTC), that allows L1 caches with bigger storage capacities while reducing the shift overhead thanks to an enhanced exploitation of spatial and temporal localities. Experimental results show that most FTC accesses do not require shifts. As a consequence, and due to its larger capacity, FTC improves the processor performance on average by 15% over a conventional SRAM memory subsystem and the state-of-the-art TapeCache architecture based on DWM. At the same time, energy savings are improved on average by 34% over the conventional design.
Navarro-Torres, Agustín; Panda, Biswabandan; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Yúfera, Víctor Viñals; Ros, Alberto
Berti: an Accurate Local-Delta Data Prefetcher Proceedings Article
En: 55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022, pp. 975–991, IEEE, 2022.
@inproceedings{DBLP:conf/micro/Navarro-TorresP22,
title = {Berti: an Accurate Local-Delta Data Prefetcher},
author = {Agustín Navarro-Torres and Biswabandan Panda and Jesús Alastruey-Benedé and Pablo Ibáñez and Víctor Viñals Yúfera and Alberto Ros},
url = {https://doi.org/10.1109/MICRO56248.2022.00072},
doi = {10.1109/MICRO56248.2022.00072},
year = {2022},
date = {2022-01-01},
booktitle = {55th IEEE/ACM International Symposium on Microarchitecture, MICRO
2022, Chicago, IL, USA, October 1-5, 2022},
pages = {975--991},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Escuin, Carlos; Khan, Asif Ali; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Castrillón, Jerónimo
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches Proceedings Article
En: DroneSE and RAPIDO ’22: System Engineering for constrained embedded systems, Budapest Hungary, January 17 – 19, 2022, pp. 53–58, ACM, 2022.
@inproceedings{DBLP:conf/hipeac/EscuinKIMVC22,
title = {HyCSim: A rapid design space exploration tool for emerging hybrid
last-level caches},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and Jerónimo Castrillón},
url = {https://doi.org/10.1145/3522784.3522801},
doi = {10.1145/3522784.3522801},
year = {2022},
date = {2022-01-01},
booktitle = {DroneSE and RAPIDO '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {53--58},
publisher = {ACM},
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Mikkelsen, Carl Christian Kjelgaard; López-Villellas, Lorién; García-Risueño, Pablo
How Accurate Does Newton Have to Be? Proceedings Article
En: International Conference on Parallel Processing and Applied Mathematics, pp. 3–15, Springer International Publishing Cham 2022.
@inproceedings{kjelgaard2022accurate,
title = {How Accurate Does Newton Have to Be?},
author = {Carl Christian Kjelgaard Mikkelsen and Lorién López-Villellas and Pablo García-Risueño},
year = {2022},
date = {2022-01-01},
booktitle = {International Conference on Parallel Processing and Applied Mathematics},
pages = {3–15},
organization = {Springer International Publishing Cham},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
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Cabo, Guillem; Candón, Gerard; Carril, Xavier; Doblas, Max; Domínguez, Marc; González, Alberto; Hernández, César; Jiménez, Víctor; Kostalampros, Vatistas; Langarita, Rubén; Leyva, Neiél; López-Paradís, Guillem; Mendoza, Jonnatan; Minervini, Francesco; Pavón, Julián; Ramírez, Cristóbal; Rodas, Narcís; Reggiani, Enrico; Rodríguez, Mario; Rojas, Carlos; Ruiz, Abraham; Soria, Víctor; Suanes, Alejandro; Vargas, Iván; Figueras, Roger; Fontova, Pau; Marimon, Joan; Montabes, Víctor; Cristal, Adrián; Hernández, Carles; Martínez, Ricardo; Moretó, Miquel; Moll, Francesc; Palomar, Oscar; Ramírez, Marco A; Rubio, Antonio; Sacristán, Jordi; Serra-Graells, Francesc; Sonmez, Nehir; Terés, Lluís; Unsal, Osman; Valero, Mateo; Villa, Luís
DVINO: A RISC-V vector processor implemented in 65nm technology Proceedings Article
En: 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), pp. 1–6, IEEE 2022.
@inproceedings{cabo2022dvino,
title = {DVINO: A RISC-V vector processor implemented in 65nm technology},
author = {Guillem Cabo and Gerard Candón and Xavier Carril and Max Doblas and Marc Domínguez and Alberto González and César Hernández and Víctor Jiménez and Vatistas Kostalampros and Rubén Langarita and Neiél Leyva and Guillem López-Paradís and Jonnatan Mendoza and Francesco Minervini and Julián Pavón and Cristóbal Ramírez and Narcís Rodas and Enrico Reggiani and Mario Rodríguez and Carlos Rojas and Abraham Ruiz and Víctor Soria and Alejandro Suanes and Iván Vargas and Roger Figueras and Pau Fontova and Joan Marimon and Víctor Montabes and Adrián Cristal and Carles Hernández and Ricardo Martínez and Miquel Moretó and Francesc Moll and Oscar Palomar and Marco A Ramírez and Antonio Rubio and Jordi Sacristán and Francesc Serra-Graells and Nehir Sonmez and Lluís Terés and Osman Unsal and Mateo Valero and Luís Villa},
url = {https://d1wqtxts1xzle7.cloudfront.net/110413773/dvino-postprint-libre.pdf?1705221936=&response-content-disposition=inline%3B+filename%3DDVINO_A_RISC_V_Vector_Processor_Implemen.pdf&Expires=1767533089&Signature=EOKaJCC8Zgn8ADQB2Lje1L04qUstPgRFdzE8E2oIYEsRYsqf8FByi4dCIS4opSN0r08ESncDVuBIFTsabFuJSenKdS2skWnr1rDGTc9jSTuZ6a-ihhfVeqv-6h~wgS2C~woOEQiPUCvUfBEKEU9eCssL74xiVC3AJ77PFW0ag0OIQGicTqLIDOUyx7Ui5WA31E2Ry-PgjukXMHgNYEgERch51YNqQwK45ezkdnrCBj3Gd8yr4e4wNUezQBQu7DEL6GTtFJoOtncLYi3RK4WKxKwYLq0ToK-mz0WBhDB1X7pOq~7PE8XQ6lRvbRnSxPsDjPc82fmuiKkN12i2Hk9Ozw__&Key-Pair-Id=APKAJLOHF5GGSLRBV4ZA},
doi = {10.1109/DCIS55711.2022.9970128},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
booktitle = {2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)},
pages = {1–6},
organization = {IEEE},
abstract = {This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.
Soria-Pardos, Víctor; Doblas, Max; López–Paradís, Guillem; Candón, Gerard; Rodas, Narcís; Carril, Xavier; Fontova–Musté, Pau; Leyva, Neiel; Marco-Sola, Santiago; Moretó, Miquel
Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI Proceedings Article
En: 2022 25th Euromicro Conference on Digital System Design (DSD), pp. 254–261, IEEE 2022.
@inproceedings{soria2022sargantana,
title = {Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI},
author = {Víctor Soria-Pardos and Max Doblas and Guillem López–Paradís and Gerard Candón and Narcís Rodas and Xavier Carril and Pau Fontova–Musté and Neiel Leyva and Santiago Marco-Sola and Miquel Moretó},
url = {https://upcommons.upc.edu/server/api/core/bitstreams/df925f8a-5a18-43ab-92c6-a448afa370dc/content},
doi = {10.1109/DSD57027.2022.00042},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
booktitle = {2022 25th Euromicro Conference on Digital System Design (DSD)},
pages = {254–261},
organization = {IEEE},
abstract = {The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sargantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sargantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.
2021
Artículos de revista
Valero, Alejandro; Tejero, Ruben Gran; Gracia, Darío Suárez; Georgescu, Emanuel A.; Ezpeleta, Joaquín; Álvarez, Pedro; Muñoz, Adolfo; Ramos, Luis M.; Ibáñez, Pablo
A learning experience toward the understanding of abstraction-level interactions in parallel applications Artículo de revista
En: J. Parallel Distributed Comput., vol. 156, pp. 38–52, 2021.
@article{DBLP:journals/jpdc/ValeroTGGEAMRI21,
title = {A learning experience toward the understanding of abstraction-level
interactions in parallel applications},
author = {Alejandro Valero and Ruben Gran Tejero and Darío Suárez Gracia and Emanuel A. Georgescu and Joaquín Ezpeleta and Pedro Álvarez and Adolfo Muñoz and Luis M. Ramos and Pablo Ibáñez},
url = {https://doi.org/10.1016/j.jpdc.2021.05.008},
doi = {10.1016/j.jpdc.2021.05.008},
year = {2021},
date = {2021-01-01},
journal = {J. Parallel Distributed Comput.},
volume = {156},
pages = {38--52},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M.
Near-optimal replacement policies for shared caches in multicore processors Artículo de revista
En: J. Supercomput., vol. 77, no 10, pp. 11756–11785, 2021.
@article{DBLP:journals/tjs/DiazIMVL21,
title = {Near-optimal replacement policies for shared caches in multicore processors},
author = {Javier Díaz and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and José M. Llabería},
url = {https://doi.org/10.1007/s11227-021-03736-1},
doi = {10.1007/s11227-021-03736-1},
year = {2021},
date = {2021-01-01},
journal = {J. Supercomput.},
volume = {77},
number = {10},
pages = {11756--11785},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Gracia, S.; Olivito, J.; Resano, J.; Martin-del-Brio, B.; Alfonso, M.; Álvarez, E.
Improving accuracy on wave height estimation through machine learning techniques Artículo de revista
En: Ocean Engineering, vol. 236, pp. 108699, 2021, ISSN: 0029-8018.
@article{GRACIA2021108699,
title = {Improving accuracy on wave height estimation through machine learning techniques},
author = {S. Gracia and J. Olivito and J. Resano and B. Martin-del-Brio and M. Alfonso and E. Álvarez},
url = {https://www.sciencedirect.com/science/article/pii/S0029801821001347},
doi = {https://doi.org/10.1016/j.oceaneng.2021.108699},
issn = {0029-8018},
year = {2021},
date = {2021-01-01},
journal = {Ocean Engineering},
volume = {236},
pages = {108699},
abstract = {Estimation of wave agitation plays a key role in predicting natural disasters, path optimization and secure harbor operation. The Spanish agency Puertos del Estado (PdE) has several oceanographic measure networks equipped with sensors for different physical variables, and manages forecast systems involving numerical models. In recent years, there is a growing interest in wave parameter estimation by using machine learning models due to the large amount of oceanographic data available for training, as well as its proven efficacy in estimating physical variables. In this study, we propose to use machine learning techniques to improve the accuracy of the current forecast system of PdE. We have focused on four physical wave variables: spectral significant height, mean spectral period, peak period and mean direction of origin. Two different machine learning models have been explored: multilayer perceptron and gradient boosting decision trees, as well as ensemble methods that combine both models. These models reduce the error of the predictions of the numerical model by 36% on average, demonstrating the potential gains of combining machine learning and numerical models.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Estimation of wave agitation plays a key role in predicting natural disasters, path optimization and secure harbor operation. The Spanish agency Puertos del Estado (PdE) has several oceanographic measure networks equipped with sensors for different physical variables, and manages forecast systems involving numerical models. In recent years, there is a growing interest in wave parameter estimation by using machine learning models due to the large amount of oceanographic data available for training, as well as its proven efficacy in estimating physical variables. In this study, we propose to use machine learning techniques to improve the accuracy of the current forecast system of PdE. We have focused on four physical wave variables: spectral significant height, mean spectral period, peak period and mean direction of origin. Two different machine learning models have been explored: multilayer perceptron and gradient boosting decision trees, as well as ensemble methods that combine both models. These models reduce the error of the predictions of the numerical model by 36% on average, demonstrating the potential gains of combining machine learning and numerical models.
Soria-Pardos, Víctor; Armejach, Adrià; Suárez, Darío; Moretó, Miquel
On the use of many-core Marvell ThunderX2 processor for HPC workloads Artículo de revista
En: The Journal of Supercomputing, vol. 77, no 4, pp. 3315–3338, 2021.
@article{soria2021use,
title = {On the use of many-core Marvell ThunderX2 processor for HPC workloads},
author = {Víctor Soria-Pardos and Adrià Armejach and Darío Suárez and Miquel Moretó},
url = {https://zaguan.unizar.es/record/112382/files/texto_completo.pdf},
doi = {10.1007/s11227-020-03397-6},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
journal = {The Journal of Supercomputing},
volume = {77},
number = {4},
pages = {3315–3338},
publisher = {Springer US New York},
abstract = {Marvell’s ThunderX2 has been the first Arm-based processor with deployments in large-scale HPC production systems, challenging the dominance that x86 processors had in the last decades. While x86 processors and its software stack have been characterized in detail, the behavior of Arm counterparts is not well known, limiting its adoption. This work methodically characterizes performance and power efficiency of the ThunderX2 running different HPC workloads compiled with two state-of-the-art compilers, GCC and Arm HPC Compiler. We study the maturity of available compilers and find that the Arm HPC Compiler is able to apply additional optimizations, resulting in better performance than GCC. In addition, we also compare both performance and power with respect to an Intel Skylake processor. Despite the faster single thread performance of Skylake, ThunderX2 is able to match performance on multi-threaded workloads due to its superior memory bandwidth. However, power efficiency of ThunderX2 is far from matching Skylake-based processors when AVX512 extensions are used.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Marvell’s ThunderX2 has been the first Arm-based processor with deployments in large-scale HPC production systems, challenging the dominance that x86 processors had in the last decades. While x86 processors and its software stack have been characterized in detail, the behavior of Arm counterparts is not well known, limiting its adoption. This work methodically characterizes performance and power efficiency of the ThunderX2 running different HPC workloads compiled with two state-of-the-art compilers, GCC and Arm HPC Compiler. We study the maturity of available compilers and find that the Arm HPC Compiler is able to apply additional optimizations, resulting in better performance than GCC. In addition, we also compare both performance and power with respect to an Intel Skylake processor. Despite the faster single thread performance of Skylake, ThunderX2 is able to match performance on multi-threaded workloads due to its superior memory bandwidth. However, power efficiency of ThunderX2 is far from matching Skylake-based processors when AVX512 extensions are used.
Alcolea, Adrián; Resano, Javier
FPGA Accelerator for Gradient Boosting Decision Trees Artículo de revista
En: Electronics, vol. 10, no 3, pp. 314, 2021.
@article{alcolea2021fpga,
title = {FPGA Accelerator for Gradient Boosting Decision Trees},
author = {Adrián Alcolea and Javier Resano},
year = {2021},
date = {2021-01-01},
journal = {Electronics},
volume = {10},
number = {3},
pages = {314},
publisher = {Multidisciplinary Digital Publishing Institute},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M
Near-optimal replacement policies for shared caches in multicore processors Artículo de revista
En: The Journal of Supercomputing, pp. 1–30, 2021.
@article{diaz2021near,
title = {Near-optimal replacement policies for shared caches in multicore processors},
author = {Javier Díaz and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and José M Llabería},
year = {2021},
date = {2021-01-01},
journal = {The Journal of Supercomputing},
pages = {1--30},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Lamela, Adrián; Ossorio, Óscar G; Vinuesa, Guillermo; Sahelices, Benjamín
Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures Artículo de revista
En: PLOS ONE, vol. 16, no 9, pp. 1-23, 2021.
@article{lamela2021offchip,
title = {Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures},
author = {Adrián Lamela and Óscar G Ossorio and Guillermo Vinuesa and Benjamín Sahelices},
url = {https://doi.org/10.1371/journal.pone.0257047},
doi = {10.1371/journal.pone.0257047},
year = {2021},
date = {2021-01-01},
journal = {PLOS ONE},
volume = {16},
number = {9},
pages = {1-23},
publisher = {Public Library of Science},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Segarra, Juan; Tejero, Ruben Gran; Viñals, Víctor
A generic framework to integrate data caches in the WCET analysis of real-time systems Artículo de revista
En: J. Syst. Archit., vol. 120, pp. 102304, 2021.
@article{DBLP:journals/jsa/SegarraTV21,
title = {A generic framework to integrate data caches in the WCET analysis of real-time systems},
author = {Juan Segarra and Ruben Gran Tejero and Víctor Viñals},
url = {https://doi.org/10.1016/j.sysarc.2021.102304},
doi = {10.1016/j.sysarc.2021.102304},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
journal = {J. Syst. Archit.},
volume = {120},
pages = {102304},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez-Marín, Pablo; Carpen-Amarie, Maria
Synchronization Strategies on Many-Core SMT Systems Proceedings Article
En: 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2021, Belo Horizonte, Brazil, October 26-29, 2021, pp. 54–63, IEEE, 2021.
@inproceedings{DBLP:conf/sbac-pad/Navarro-TorresA21,
title = {Synchronization Strategies on Many-Core SMT Systems},
author = {Agustín Navarro-Torres and Jesús Alastruey-Benedé and Pablo Ibáñez-Marín and Maria Carpen-Amarie},
url = {https://doi.org/10.1109/SBAC-PAD53543.2021.00017},
doi = {10.1109/SBAC-PAD53543.2021.00017},
year = {2021},
date = {2021-01-01},
booktitle = {33rd IEEE International Symposium on Computer Architecture and High
Performance Computing, SBAC-PAD 2021, Belo Horizonte, Brazil, October
26-29, 2021},
pages = {54--63},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2020
Artículos de revista
Valero, Alejandro; Gracia, Darío Suárez; Tejero, Rubén Gran
DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files Artículo de revista
En: IEEE Access, vol. 8, pp. 173276-173288, 2020, ISSN: 2169-3536.
@article{Valero2020,
title = {DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files},
author = {Alejandro Valero and Darío Suárez Gracia and Rubén Gran Tejero},
url = {https://ieeexplore.ieee.org/document/9203907},
doi = {https://doi.org/10.1109/ACCESS.2020.3025899},
issn = {2169-3536},
year = {2020},
date = {2020-09-22},
urldate = {2020-09-22},
journal = {IEEE Access},
volume = {8},
pages = {173276-173288},
abstract = {The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.