Computer Architect and Teaching Assistant
Email: victor.soria.pardos@upc.edu
Address: Campus Nord, Polytechnic University of Catalonia
C/Jordi Girona, 1-3, B6 Building
08034 Barcelona (Spain)
ABOUT ME
Víctor Soria Pardos received the BSc degree in Computer Science from the Universidad de Zaragoza, Spain, in 2019 and the MSc and the PhD degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC), Spain, in 2022 and 2026, respectively. Currently, he is a Teaching Assistant with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. His research interests include processor microarchitecture, memory hierarchy, cache coherence and parallel computer architecture. He collaborates actively with the Grupo de Arquitectura de Computadores from the Universidad de Zaragoza (gaZ).
PUBLICATIONS
2020
Proceedings Articles
Abella, Jaume; Bulla, Calvin; Cabo, Guillem; Cazorla, Francisco J; Cristal, Adrián; Doblas, Max; Figueras, Roger; González, Alberto; Hernández, Carles; Hernández, César; Jiménez, Víctor; Kosmidis, Leonidas; Kostalabros, Vatistas; Langarita, Rubén; Leyva, Neiel; López-Paradís, Guillem; Marimon, Joan; Martínez, Ricardo; Mendoza, Jonnatan; Moll, Francesc; Moretó, Miquel; Pavón, Julián; Ramírez, Cristóbal; Ramírez, Marco A; Rojas, Carlos; Rubio, Antonio; Ruiz, Abraham; Sonmez, Nehir; Soria, Víctor; Terés, Lluís; Unsal, Osman; Valero, Mateo; Vargas, Iván; Villa, Luis; Ramííez, Cristóbal
An academic risc-v silicon implementation based on open-source components Proceedings Article
En: 2020 XXXV conference on design of circuits and integrated systems (DCIS), pp. 1–6, IEEE 2020.
@inproceedings{abella2020academic,
title = {An academic risc-v silicon implementation based on open-source components},
author = {Jaume Abella and Calvin Bulla and Guillem Cabo and Francisco J Cazorla and Adrián Cristal and Max Doblas and Roger Figueras and Alberto González and Carles Hernández and César Hernández and Víctor Jiménez and Leonidas Kosmidis and Vatistas Kostalabros and Rubén Langarita and Neiel Leyva and Guillem López-Paradís and Joan Marimon and Ricardo Martínez and Jonnatan Mendoza and Francesc Moll and Miquel Moretó and Julián Pavón and Cristóbal Ramírez and Marco A Ramírez and Carlos Rojas and Antonio Rubio and Abraham Ruiz and Nehir Sonmez and Víctor Soria and Lluís Terés and Osman Unsal and Mateo Valero and Iván Vargas and Luis Villa and Cristóbal Ramííez},
url = {https://d1wqtxts1xzle7.cloudfront.net/109321567/DCIS2020_PreDRAC_PostPrint-libre.pdf?1703100672=&response-content-disposition=inline%3B+filename%3DAn_Academic_RISC_V_Silicon_Implementatio.pdf&Expires=1767532917&Signature=PWJAucQ3fP2kF7S5J4WalI6b~NNg6CjDDYlDr~1g5EuQ3ZaC-sSvkQ7FGnqAJDAgbkNHnaqaGK~5OHsCHVHkq2g45nI5-5NSxhaGk76LvFxE3LwpcU6hzTTHBwyBw1J6Bt54L6M1lPRECkRmB-Nm---l0FPo0Q6aiZaIM~sguZ4ZMofBcN0-szbGhV2Ntv5qb6Qg0ly4Km9oFE7JWQyHGcazipoiR6onp3s0zsG1Sb3wLrTcvFZ9VhpajkHyUDuIIbks8AO81jR8ts~N7-OxSteF9cRh4-hvYibUhQFh3GmEVFx11NDrDfI4jFoCJ8zrfMrElZIX3IkJrjxEaWckOQ__&Key-Pair-Id=APKAJLOHF5GGSLRBV4ZA},
doi = {10.1109/DCIS51330.2020.9268664},
year = {2020},
date = {2020-01-01},
urldate = {2020-01-01},
booktitle = {2020 XXXV conference on design of circuits and integrated systems (DCIS)},
pages = {1–6},
organization = {IEEE},
abstract = {The design presented, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
0000
Proceedings Articles
Oliete-Escuín, Noelia; Bigas-Soldevila, Arnau; Rodas, Narcís; Aguilera, Albert; Ahmad, Sajjad; Balkind, Jonathan; Carril, Xavier; Doblas, Max; Díaz, Iván; Figueras, Roger; Foroodnia, Alireza; Fuget, Cesar; Genovese, Ignacio; Gilabert, Raúl; Haghi, Abbas; Kropotov, Alexander; Leyva, Neiel; Lostes-Cazorla, Oscar; López-Villellas, Lorién; Million, Davy; Monemi, Alireza; Pérez, S.; Rodríguez, Juan Antonio; Soria-Pardos, Víctor; Salami, Behzad; Moll, Francesc; Palomar, Oscar; Moretó, Miquel; Alvarez, Lluc
REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton Proceedings Article
En: 0000.
@inproceedings{OlieteEscunREPTILESRT,
title = {REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton},
author = {Noelia Oliete-Escuín and Arnau Bigas-Soldevila and Narcís Rodas and Albert Aguilera and Sajjad Ahmad and Jonathan Balkind and Xavier Carril and Max Doblas and Iván Díaz and Roger Figueras and Alireza Foroodnia and Cesar Fuget and Ignacio Genovese and Raúl Gilabert and Abbas Haghi and Alexander Kropotov and Neiel Leyva and Oscar Lostes-Cazorla and Lorién López-Villellas and Davy Million and Alireza Monemi and S. Pérez and Juan Antonio Rodríguez and Víctor Soria-Pardos and Behzad Salami and Francesc Moll and Oscar Palomar and Miquel Moretó and Lluc Alvarez},
url = {https://api.semanticscholar.org/CorpusID:283146120},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}