{"id":3701,"date":"2023-01-23T13:43:12","date_gmt":"2023-01-23T11:43:12","guid":{"rendered":"https:\/\/gaz-temporal.i3a.es\/?p=3701"},"modified":"2023-01-24T11:23:05","modified_gmt":"2023-01-24T09:23:05","slug":"ruben-gran-tejero","status":"publish","type":"post","link":"https:\/\/gaz.i3a.es\/es\/ruben-gran-tejero\/","title":{"rendered":"Rub\u00e9n Gran Tejero"},"content":{"rendered":"
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    Investigadores<\/a><\/h3>\n

    Rub\u00e9n Gran Tejero<\/strong><\/h1>\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<\/li>\n\t\t<\/ul>\t\t\t\t
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      Senior Lecturer<\/strong><\/p>\n

      Email:<\/strong> rgran@unizar.es<\/a><\/p>\n

      Address:<\/strong> Campus R\u00edo Ebro, University of Zaragoza
      \nC\/Mar\u00eda de Luna 1, Ada Byron Building,
      \n50018, Zaragoza, Spain<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n

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      Rub\u00e9n Gran Tejero graduated in Computer Science from the University of Zaragoza, Spain. He received his Ph.D. from the Polytechnic University of Catalonia (UPC), Spain, in 2010. Since 2010, he has been an Associate Professor at the Department of Computer Science and Systems Engineering, University of Zaragoza. His research interests include hard real-time systems, hardware for reducing worst-case execution time and energy consumption, efficient processor microarchitecture, and effective programming for parallel and heterogeneous systems. Dr. Gran Tejero is member of the Aragon Institute of Engineering Research (I3A) and the Spanish Society of Computer Architecture (SARTECO).<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>

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      50 registros<\/span> «<\/a> ‹<\/a> 1 de 10 ›<\/a> »<\/a> <\/div><\/div>

      2024<\/h3>

      Art\u00edculos de revista<\/h3>

      Toca-D\u00edaz, Yamilka; Tejero, Rub\u00e9n Gran; Valero, Alejandro<\/p>

      Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators<\/a> Art\u00edculo de revista<\/span> <\/p>

      En: <\/span>Journal of Systems Architecture, <\/span>vol. 157, <\/span>pp. 1-13, <\/span>2024<\/span>, ISSN: 1383-7621<\/span>.<\/p>

      Resumen<\/a><\/span> | Enlaces<\/a><\/span> | BibTeX<\/a><\/span><\/p>

      @article{Toca-D\u00edaz2024,
      \r\ntitle = {Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators},
      \r\nauthor = {Yamilka Toca-D\u00edaz and Rub\u00e9n Gran Tejero and Alejandro Valero},
      \r\nurl = {https:\/\/www.sciencedirect.com\/science\/article\/pii\/S1383762124002297},
      \r\ndoi = {https:\/\/doi.org\/10.1016\/j.sysarc.2024.103292},
      \r\nissn = {1383-7621},
      \r\nyear  = {2024},
      \r\ndate = {2024-12-01},
      \r\nurldate = {2024-12-01},
      \r\njournal = {Journal of Systems Architecture},
      \r\nvolume = {157},
      \r\npages = {1-13},
      \r\nabstract = {Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low Vdd voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at Vmin, respectively.},
      \r\nkeywords = {},
      \r\npubstate = {published},
      \r\ntppubtype = {article}
      \r\n}
      \r\n<\/pre><\/div>
      Cerrar<\/a><\/p><\/div>
      Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low Vdd voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at Vmin, respectively.<\/div>
      Cerrar<\/a><\/p><\/div>