{"id":3713,"date":"2023-01-23T15:11:27","date_gmt":"2023-01-23T13:11:27","guid":{"rendered":"https:\/\/gaz-temporal.i3a.es\/?p=3713"},"modified":"2023-01-23T15:39:24","modified_gmt":"2023-01-23T13:39:24","slug":"maria-villarroya-gaudo","status":"publish","type":"post","link":"https:\/\/gaz.i3a.es\/es\/maria-villarroya-gaudo\/","title":{"rendered":"Mar\u00eda Villarroya Gaud\u00f3"},"content":{"rendered":"
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    Investigadores<\/a><\/h3>\n

    Mar\u00eda Villarroya Gaud\u00f3<\/strong><\/h1>\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<\/li>\n\t\t<\/ul>\t\t\t\t
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      Senior Lecturer<\/strong><\/p>\n

      Email:<\/strong> mvg@unizar.es<\/a><\/p>\n

      Address:<\/strong> Campus R\u00edo Ebro, University of Zaragoza
      \nC\/Mar\u00eda de Luna 1, Ada Byron Building,
      \n50018, Zaragoza, Spain<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n

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      Mar\u00eda Villarroya Gaud\u00f3 obtained her Ph.D. in 2005 at the Department of Electronics Engineering at the Autonoma University of Barcelona. She is an Associate Professor in Computer Architecture and Technology in the Department of Computer and Systems Engineering at the Universidad de Zaragoza. Her research interests include memory hierarchy and heterogeneous systems. Dr. Vilarroya-Gaud\u00f3 is member of the Aragon Institute of Engineering Research (I3A), the Spanish Society of Computer Architecture (SARTECO).<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>

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      41 registros<\/span> «<\/a> ‹<\/a> 1 de 9 ›<\/a> »<\/a> <\/div><\/div>

      2022<\/h3>

      Proceedings Articles<\/h3>

      Gracia, Dar\u00edo Su\u00e1rez; Valero, Alejandro; Tejero, Rub\u00e9n Gran; Villarroya-Gaud\u00f3, Mar\u00eda; Vi\u00f1als, V\u00edctor<\/p>

      peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter<\/a> Proceedings Article<\/span> <\/p>

      En: <\/span>Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022), <\/span>pp. 1-6, <\/span>2022<\/span>, ISBN: 978-1-6654-5950-1<\/span>.<\/p>

      Resumen<\/a><\/span> | Enlaces<\/a><\/span> | BibTeX<\/a><\/span><\/p>

      @inproceedings{Gracia2022,
      \r\ntitle = {peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter},
      \r\nauthor = {Dar\u00edo Su\u00e1rez Gracia and Alejandro Valero and Rub\u00e9n Gran Tejero and Mar\u00eda Villarroya-Gaud\u00f3 and V\u00edctor Vi\u00f1als},
      \r\nurl = {https:\/\/ieeexplore.ieee.org\/document\/9970050},
      \r\ndoi = {https:\/\/doi.org\/10.1109\/DCIS55711.2022.9970050},
      \r\nisbn = {978-1-6654-5950-1},
      \r\nyear  = {2022},
      \r\ndate = {2022-11-16},
      \r\nurldate = {2022-11-16},
      \r\nbooktitle = {Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022)},
      \r\npages = {1-6},
      \r\nabstract = {The fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience.},
      \r\nkeywords = {},
      \r\npubstate = {published},
      \r\ntppubtype = {inproceedings}
      \r\n}
      \r\n<\/pre><\/div>
      Cerrar<\/a><\/p><\/div>
      The fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience.<\/div>
      Cerrar<\/a><\/p><\/div>