{"id":3774,"date":"2023-01-24T10:06:02","date_gmt":"2023-01-24T08:06:02","guid":{"rendered":"https:\/\/gaz-temporal.i3a.es\/?p=3774"},"modified":"2023-01-24T10:12:04","modified_gmt":"2023-01-24T08:12:04","slug":"dario-suarez-gracia","status":"publish","type":"post","link":"https:\/\/gaz.i3a.es\/es\/dario-suarez-gracia\/","title":{"rendered":"Dar\u00edo Suarez Gracia"},"content":{"rendered":"
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    Investigadores<\/a><\/h3>\n

    Dar\u00edo Suarez Gracia<\/strong><\/h1>\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<\/li>\n\t\t<\/ul>\t\t\t\t
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      Senior Lecturer<\/strong><\/p>\n

      Email:<\/strong> dario@unizar.es<\/a><\/p>\n

      Address:<\/strong> Campus R\u00edo Ebro, University of Zaragoza
      \nC\/Mar\u00eda de Luna 1, Ada Byron Building,
      \n50018, Zaragoza, Spain<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n

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      66 registros<\/span> «<\/a> ‹<\/a> 1 de 14 ›<\/a> »<\/a> <\/div><\/div>

      2025<\/h3>

      Art\u00edculos de revista<\/h3>

      Pedrajas, Samuel P\u00e9rez; Resano, Javier; Gracia, Dar\u00edo Su\u00e1rez<\/p>

      BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores<\/a> Art\u00edculo de revista<\/span> <\/p>

      En: <\/span>IEEE Transactions on Circuits and Systems for Artificial Intelligence, <\/span>pp. 1-12, <\/span>2025<\/span>, ISSN: 2996-6647<\/span>.<\/p>

      Resumen<\/a><\/span> | Enlaces<\/a><\/span> | BibTeX<\/a><\/span><\/p>

      @article{11216142,
      \r\ntitle = {BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores},
      \r\nauthor = {Samuel P\u00e9rez Pedrajas and Javier Resano and Dar\u00edo Su\u00e1rez Gracia},
      \r\ndoi = {10.1109\/TCASAI.2025.3625517},
      \r\nissn = {2996-6647},
      \r\nyear  = {2025},
      \r\ndate = {2025-01-01},
      \r\njournal = {IEEE Transactions on Circuits and Systems for Artificial Intelligence},
      \r\npages = {1-12},
      \r\nabstract = {Bayesian Neural Networks (BNN) allow prediction uncertainty estimation, making them a more suitable option for safety-critical applications. However, in BNNs, the forward-pass computational cost is significantly higher than in traditional neural networks (NN), due to the overhead generated by weight sampling. This limits their deployment in edge systems. This paper presents an optimization that allows using lower-cost Uniform distribution sampling instead of Gaussian sampling during BNN inference. Building upon this optimization, this paper proposes a lightweight RISC-V instruction set architecture extension that accelerates BNN inference by introducing fixed point arithmetic operations and an efficient Uniform random number generator. The flexibility of RISC-V enables such domain-specific acceleration, narrowing the performance gap between NNs and BNNs for edge machine learning workloads. The proposed software and hardware optimizations achieve an average speedup of 8.93\u00d7 while reducing energy consumption per forward pass by 87.12%, increasing image\/J efficiency by 8.19\u00d7. They have been designed to maintain accuracy, calibration, and uncertainty quality, while optimizing execution efficiency. This has been verified with an extensive validation process that considers relevant model architectures. Additionally, our results highlight that weight sampling is no longer the BNN inference performance bottleneck, shifting the primary limiting factor to control overhead.},
      \r\nkeywords = {},
      \r\npubstate = {published},
      \r\ntppubtype = {article}
      \r\n}
      \r\n<\/pre><\/div>
      Cerrar<\/a><\/p><\/div>
      Bayesian Neural Networks (BNN) allow prediction uncertainty estimation, making them a more suitable option for safety-critical applications. However, in BNNs, the forward-pass computational cost is significantly higher than in traditional neural networks (NN), due to the overhead generated by weight sampling. This limits their deployment in edge systems. This paper presents an optimization that allows using lower-cost Uniform distribution sampling instead of Gaussian sampling during BNN inference. Building upon this optimization, this paper proposes a lightweight RISC-V instruction set architecture extension that accelerates BNN inference by introducing fixed point arithmetic operations and an efficient Uniform random number generator. The flexibility of RISC-V enables such domain-specific acceleration, narrowing the performance gap between NNs and BNNs for edge machine learning workloads. The proposed software and hardware optimizations achieve an average speedup of 8.93\u00d7 while reducing energy consumption per forward pass by 87.12%, increasing image\/J efficiency by 8.19\u00d7. They have been designed to maintain accuracy, calibration, and uncertainty quality, while optimizing execution efficiency. This has been verified with an extensive validation process that considers relevant model architectures. Additionally, our results highlight that weight sampling is no longer the BNN inference performance bottleneck, shifting the primary limiting factor to control overhead.<\/div>
      Cerrar<\/a><\/p><\/div>