{"id":3810,"date":"2023-01-24T10:33:32","date_gmt":"2023-01-24T08:33:32","guid":{"rendered":"https:\/\/gaz-temporal.i3a.es\/?p=3810"},"modified":"2025-05-05T14:50:01","modified_gmt":"2025-05-05T12:50:01","slug":"carlos-escuin-blasco","status":"publish","type":"post","link":"https:\/\/gaz.i3a.es\/es\/carlos-escuin-blasco\/","title":{"rendered":"Carlos Escu\u00edn Blasco"},"content":{"rendered":"
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    Investigadores<\/a><\/h3>\n

    Carlos Escu\u00edn Blasco<\/strong><\/h1>\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<\/li>\n\t\t<\/ul>\t\t\t\t
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      PhD student<\/strong><\/p>\n

      Email:<\/strong> escuin@unizar.es<\/a><\/p>\n

      Address:<\/strong> Campus R\u00edo Ebro, University of Zaragoza
      \nC\/Mar\u00eda de Luna 1, Ada Byron Building,
      \n50018, Zaragoza, Spain<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n

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      —<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>

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      2019<\/h3>

      Proceedings Articles<\/h3>

      Blasco, Carlos Escu\u00edn; Arnal, Teresa Monreal; Gri\u00f1\u00f3, Jos\u00e9 M Llaberia; Y\u00fafera, Victor Vi\u00f1als; Mar\u00edn, Pablo Ib\u00e1\u00f1ez<\/p>

      STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption Proceedings Article<\/span> <\/p>

      En: <\/span>ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts, <\/span>pp. 231\u2013234, <\/span>European Network of Excellence on High Performance and Embedded Architecture~\u2026 <\/span>2019<\/span>.<\/p>

      BibTeX<\/a><\/span><\/p>

      @inproceedings{escuin2019stt,
      \r\ntitle = {STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption},
      \r\nauthor = {Carlos Escu\u00edn Blasco and Teresa Monreal Arnal and Jos\u00e9 M Llaberia Gri\u00f1\u00f3 and Victor Vi\u00f1als Y\u00fafera and Pablo Ib\u00e1\u00f1ez Mar\u00edn},
      \r\nyear  = {2019},
      \r\ndate = {2019-01-01},
      \r\nbooktitle = {ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts},
      \r\npages = {231--234},
      \r\norganization = {European Network of Excellence on High Performance and Embedded Architecture~\u2026},
      \r\nkeywords = {},
      \r\npubstate = {published},
      \r\ntppubtype = {inproceedings}
      \r\n}
      \r\n<\/pre><\/div>
      Cerrar<\/a><\/p><\/div><\/div><\/div><\/div><\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div><\/div>\n\n\n
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