{"id":3835,"date":"2023-01-24T11:35:37","date_gmt":"2023-01-24T09:35:37","guid":{"rendered":"https:\/\/gaz-temporal.i3a.es\/?p=3835"},"modified":"2025-12-23T01:20:28","modified_gmt":"2025-12-22T23:20:28","slug":"alejandro-valero","status":"publish","type":"post","link":"https:\/\/gaz.i3a.es\/es\/alejandro-valero\/","title":{"rendered":"Alejandro Valero"},"content":{"rendered":"
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    Investigadores<\/a><\/h3>\n

    Alejandro Valero<\/strong><\/h1>\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<\/li>\n\t\t<\/ul>\t\t\t\t
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       <\/p>\n

      Associate Professor<\/strong><\/p>\n

      Email:<\/strong> alvabre@unizar.es<\/a><\/p>\n

      Address:<\/strong>
      \nDepartment of Computer Science and Systems Engineering
      \nUniversidad de Zaragoza
      \nCalle Mar\u00eda de Luna, 1
      \nAda Byron Building
      \n50018 Zaragoza, Spain<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n

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      Alejandro Valero received the BS, MS, and PhD degrees in Computer Engineering from the Universitat Polit\u00e8cnica de Val\u00e8ncia<\/em>, Spain, in 2009, 2011, and 2013, respectively. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston (MA), USA, and the University of Cambridge, UK. From 2016 to 2021 he was an Assistant Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza<\/em>, Spain. Since 2021 he is an Associate Professor with the same department and institution. Prof. Valero has taught several courses on computer organization, including digital design, computer organization and design, heterogeneous systems programming and design, data center design, and operating systems. His PhD research contributions to the design of high-performance, energy-efficient CPU memory subsystems were recognized by multiple entities. He received the Intel Doctoral Student Honor Program Award in 2012 and the Gold Medal in the ACM Student Research Competition (SRC) held in the 27th International Conference on Supercomputing (ICS 2013). His research interests mainly focus on the design of memory hierarchies in terms of performance, energy efficiency, and reliability for different microprocessors: CPU systems, general-purpose GPUs, and accelerators for computer vision algorithms. Prof. Valero has participated in more than 20 national and local funded research projects and has published more than 30 papers in the main venues of the computer architecture area, such as the IEEE\/ACM International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), IEEE Transactions on Computers, and IEEE Transactions on Very Large Scale Integration (VLSI) Systems. He has served as Technical Program Committee member in a significant number of conferences, workshops, and research competitions, like the Design Automation and Test in Europe (DATE) conference, the IEEE International Conference on Computer Design (ICCD), the Performance Modeling, Benchmarking, and Simulation of High Performance Computer Systems (PMBS) workshop, and the ACM SRC Grand Finals. He is also a frequent reviewer in top journals of his area, such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Dependable and Secure Computing, and ACM Transactions on Design Automation of Electronic Systems. He was a recipient of the Outstanding Reviewer Award in the Design Methods and Tools track at the DATE 2024 conference. Prof. Valero is a member of the ACM, the Sociedad de Arquitectura y Tecnolog\u00eda de Computadores<\/em> (SARTECO), the Aragon Institute of Engineering Research (I3A), and an affiliated member of the High Performance, Edge, And Cloud Computing (HiPEAC) European Network of Excellence.<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>

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      41 registros<\/span> «<\/a> ‹<\/a> 1 de 9 ›<\/a> »<\/a> <\/div><\/div>

      2025<\/h3>

      Art\u00edculos de revista<\/h3>

      Valero, Alejandro; Lorente, Vicente; Petit, Salvador; Sahuquillo, Julio<\/p>

      Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches<\/a> Art\u00edculo de revista<\/span> <\/p>

      En: <\/span>IEEE Transactions on Computers, <\/span>vol. 74, <\/span>no 8, <\/span>pp. 2812-2826, <\/span>2025<\/span>, ISSN: 0018-9340<\/span>.<\/p>

      Resumen<\/a><\/span> | Enlaces<\/a><\/span> | BibTeX<\/a><\/span><\/p>

      @article{Valero2025,
      \r\ntitle = {Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches},
      \r\nauthor = {Alejandro Valero and Vicente Lorente and Salvador Petit and Julio Sahuquillo},
      \r\nurl = {https:\/\/www.computer.org\/csdl\/journal\/tc\/2025\/08\/11022726\/27fzlt4rw88},
      \r\ndoi = {10.1109\/TC.2025.3575909},
      \r\nissn = {0018-9340},
      \r\nyear  = {2025},
      \r\ndate = {2025-08-01},
      \r\nurldate = {2025-08-01},
      \r\njournal = {IEEE Transactions on Computers},
      \r\nvolume = {74},
      \r\nnumber = {8},
      \r\npages = {2812-2826},
      \r\nabstract = {Static Random-Access Memory (SRAM) is the fastest memory technology and has been the common design choice for implementing first-level (L1) caches in the processor pipeline, where speed is a key design issue that must be fulfilled. On the contrary, this technology offers much lower density compared to other technologies like Dynamic RAM, limiting L1 cache sizes of modern processors to a few tens of KB. This paper explores the use of slower but denser Domain Wall Memory (DWM) technology for L1 caches. This technology provides slow access times since it arranges multiple bits sequentially in a magnetic racetrack. To access these bits, they need to be shifted in order to place them under a header. A 1-bit shift usually takes one processor cycle, which can significantly hurt the application performance, making this working behavior inappropriate for L1 caches. Based on the locality (temporal and spatial) principles exploited by caches, this work proposes the Dual Fast-Track Cache (Dual FTC) design, a new approach to organizing a set of racetracks to build set-associative caches. Compared to a conventional SRAM cache, Dual FTC enhances storage capacity by 5\u00d7 while incurring minimal shifting overhead, thereby rendering it a practical and appealing solution for L1 cache implementations. Experimental results show that the devised cache organization is as fast as an SRAM cache for 78% and 86% of the L1 data cache hits and L1 instruction cache hits, respectively (i.e., no shift is required). Consequently, due to the larger L1 cache capacities, significant system performance gains (by 22% on average) are obtained under the same silicon area.},
      \r\nkeywords = {},
      \r\npubstate = {published},
      \r\ntppubtype = {article}
      \r\n}
      \r\n<\/pre><\/div>
      Cerrar<\/a><\/p><\/div>
      Static Random-Access Memory (SRAM) is the fastest memory technology and has been the common design choice for implementing first-level (L1) caches in the processor pipeline, where speed is a key design issue that must be fulfilled. On the contrary, this technology offers much lower density compared to other technologies like Dynamic RAM, limiting L1 cache sizes of modern processors to a few tens of KB. This paper explores the use of slower but denser Domain Wall Memory (DWM) technology for L1 caches. This technology provides slow access times since it arranges multiple bits sequentially in a magnetic racetrack. To access these bits, they need to be shifted in order to place them under a header. A 1-bit shift usually takes one processor cycle, which can significantly hurt the application performance, making this working behavior inappropriate for L1 caches. Based on the locality (temporal and spatial) principles exploited by caches, this work proposes the Dual Fast-Track Cache (Dual FTC) design, a new approach to organizing a set of racetracks to build set-associative caches. Compared to a conventional SRAM cache, Dual FTC enhances storage capacity by 5\u00d7 while incurring minimal shifting overhead, thereby rendering it a practical and appealing solution for L1 cache implementations. Experimental results show that the devised cache organization is as fast as an SRAM cache for 78% and 86% of the L1 data cache hits and L1 instruction cache hits, respectively (i.e., no shift is required). Consequently, due to the larger L1 cache capacities, significant system performance gains (by 22% on average) are obtained under the same silicon area.<\/div>
      Cerrar<\/a><\/p><\/div>