{"id":4152,"date":"2026-01-04T12:49:10","date_gmt":"2026-01-04T10:49:10","guid":{"rendered":"https:\/\/gaz.i3a.es\/?p=4152"},"modified":"2026-01-04T14:10:58","modified_gmt":"2026-01-04T12:10:58","slug":"victor-soria-pardos","status":"publish","type":"post","link":"https:\/\/gaz.i3a.es\/es\/victor-soria-pardos\/","title":{"rendered":"V\u00edctor Soria Pardos"},"content":{"rendered":"<div id=\"pl-gb4152-69f241488d9c8\"  class=\"panel-layout wp-block-siteorigin-panels-layout-block\" ><div id=\"pg-gb4152-69f241488d9c8-0\"  class=\"panel-grid panel-has-style\" ><div class=\"siteorigin-panels-stretch panel-row-style panel-row-style-for-gb4152-69f241488d9c8-0\" data-stretch-type=\"full-width-stretch\" ><div id=\"pgc-gb4152-69f241488d9c8-0-0\"  class=\"panel-grid-cell\" ><div id=\"panel-gb4152-69f241488d9c8-0-0-0\" class=\"so-panel widget widget_sow-hero panel-first-child panel-last-child\" data-index=\"0\" ><div\n\t\t\t\n\t\t\tclass=\"so-widget-sow-hero so-widget-sow-hero-default-7a011a7c0fd5-4152 so-widget-fittext-wrapper\"\n\t\t\t data-fit-text-compressor=\"0.85\"\n\t\t>\t\t\t\t<div class=\"sow-slider-base\" style=\"display: none\" tabindex=\"0\">\n\t\t\t\t\t<ul\n\t\t\t\t\tclass=\"sow-slider-images\"\n\t\t\t\t\tdata-settings=\"{&quot;pagination&quot;:true,&quot;speed&quot;:800,&quot;timeout&quot;:8000,&quot;paused&quot;:false,&quot;pause_on_hover&quot;:false,&quot;swipe&quot;:true,&quot;nav_always_show_desktop&quot;:&quot;&quot;,&quot;nav_always_show_mobile&quot;:&quot;&quot;,&quot;breakpoint&quot;:&quot;780px&quot;,&quot;unmute&quot;:false,&quot;anchor&quot;:null}\"\n\t\t\t\t\t\t\t\t\t\tdata-anchor-id=\"\"\n\t\t\t\t>\t\t<li class=\"sow-slider-image\" style=\"visibility: visible;;background-color: #1e73be\" >\n\t\t\t\t\t<div class=\"sow-slider-image-container\">\n\t\t\t<div class=\"sow-slider-image-wrapper\">\n\t\t\t\t<h3 style=\"text-align: center\"><a href=\"..\/team\/\">Investigadores<\/a><\/h3>\n<h1 style=\"text-align: center\"><strong>V\u00edctor Soria Pardos<\/strong><\/h1>\n\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<\/li>\n\t\t<\/ul>\t\t\t\t<ol class=\"sow-slider-pagination\">\n\t\t\t\t\t\t\t\t\t\t\t<li><a href=\"#\" data-goto=\"0\" aria-label=\"mostrar diapositiva 1\"><\/a><\/li>\n\t\t\t\t\t\t\t\t\t<\/ol>\n\n\t\t\t\t<div class=\"sow-slide-nav sow-slide-nav-next\">\n\t\t\t\t\t<a href=\"#\" data-goto=\"next\" aria-label=\"diapositiva siguiente\" data-action=\"next\">\n\t\t\t\t\t\t<em class=\"sow-sld-icon-thin-right\"><\/em>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\n\t\t\t\t<div class=\"sow-slide-nav sow-slide-nav-prev\">\n\t\t\t\t\t<a href=\"#\" data-goto=\"previous\" aria-label=\"diapositiva anterior\" data-action=\"prev\">\n\t\t\t\t\t\t<em class=\"sow-sld-icon-thin-left\"><\/em>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div><\/div><\/div><\/div><\/div><\/div><\/div>\n\n<div id=\"pl-gb4152-69f241488e367\"  class=\"panel-layout wp-block-siteorigin-panels-layout-block\" ><div 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https:\/\/gaz.i3a.es\/wp-content\/uploads\/2020\/10\/google-scholar-12x12.png 12w\" sizes=\"auto, (max-width: 37px) 100vw, 37px\" \/>\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<div class=\"sow-image-grid-image\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<a href=\"https:\/\/vsoriap.github.io\/\"\n\t\t\t\t\t>\n\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"37\" height=\"37\" src=\"https:\/\/gaz.i3a.es\/wp-content\/uploads\/2020\/10\/web.png\" class=\"sow-image-grid-image_html\" alt=\"\" title=\"\" srcset=\"https:\/\/gaz.i3a.es\/wp-content\/uploads\/2020\/10\/web.png 37w, https:\/\/gaz.i3a.es\/wp-content\/uploads\/2020\/10\/web-12x12.png 12w\" sizes=\"auto, (max-width: 37px) 100vw, 37px\" \/>\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<div class=\"sow-image-grid-image\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<a href=\"https:\/\/orcid.org\/0000-0001-8337-6326\"\n\t\t\t\t\t>\n\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"37\" height=\"37\" src=\"https:\/\/gaz.i3a.es\/wp-content\/uploads\/2023\/01\/orcid_icon.png\" class=\"sow-image-grid-image_html\" alt=\"\" title=\"\" srcset=\"https:\/\/gaz.i3a.es\/wp-content\/uploads\/2023\/01\/orcid_icon.png 37w, https:\/\/gaz.i3a.es\/wp-content\/uploads\/2023\/01\/orcid_icon-12x12.png 12w\" sizes=\"auto, (max-width: 37px) 100vw, 37px\" \/>\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t<\/div>\n<\/div><\/div><\/div><div id=\"panel-gb4152-69f241488e367-0-1-1\" class=\"so-panel widget widget_sow-editor panel-last-child\" data-index=\"2\" ><div\n\t\t\t\n\t\t\tclass=\"so-widget-sow-editor so-widget-sow-editor-base\"\n\t\t\t\n\t\t>\n<div class=\"siteorigin-widget-tinymce textwidget\">\n\t<p><strong>Computer Architect and Teaching Assistant<\/strong><\/p>\n<p><strong>Email:<\/strong> <a href=\"mailto:victor.soria.pardos@upc.edu\">victor.soria.pardos@upc.edu<\/a><\/p>\n<p><strong>Address:<\/strong> Campus Nord, Polytechnic University of Catalonia<br \/>\nC\/Jordi Girona, 1-3, B6 Building<br \/>\n08034 Barcelona (Spain)<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n<div id=\"pl-gb4152-69f241488ff62\"  class=\"panel-layout wp-block-siteorigin-panels-layout-block\" ><div id=\"pg-gb4152-69f241488ff62-0\"  class=\"panel-grid panel-has-style\" ><div class=\"panel-row-style panel-row-style-for-gb4152-69f241488ff62-0\" ><div id=\"pgc-gb4152-69f241488ff62-0-0\"  class=\"panel-grid-cell\" ><div id=\"panel-gb4152-69f241488ff62-0-0-0\" class=\"so-panel widget widget_sow-headline panel-first-child\" data-index=\"0\" ><div\n\t\t\t\n\t\t\tclass=\"so-widget-sow-headline so-widget-sow-headline-default-244eb6bef45a-4152\"\n\t\t\t\n\t\t><div class=\"sow-headline-container\">\n\t\t\t\t\t\t\t<h5 class=\"sow-headline\">\n\t\t\t\t\t\tABOUT ME\t\t\t\t\t\t<\/h5>\n\t\t\t\t\t\t\t\t\t\t\t<div class=\"decoration\">\n\t\t\t\t\t\t<div class=\"decoration-inside\"><\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n<\/div><\/div><div id=\"panel-gb4152-69f241488ff62-0-0-1\" class=\"so-panel widget widget_sow-editor panel-last-child\" data-index=\"1\" ><div\n\t\t\t\n\t\t\tclass=\"so-widget-sow-editor so-widget-sow-editor-base\"\n\t\t\t\n\t\t>\n<div class=\"siteorigin-widget-tinymce textwidget\">\n\t<p>V\u00edctor Soria Pardos received the BSc degree in Computer Science from the Universidad de Zaragoza, Spain, in 2019 and the MSc and the PhD degree in Computer Engineering from the Universitat Polit\u00e8cnica de Catalunya (UPC), Spain, in 2022 and 2026, respectively. Currently, he is a Teaching Assistant with the Computer Architecture Department (DAC) at the Universitat Polit\u00e8cnica de Catalunya (UPC), Spain. His research interests include processor microarchitecture, memory hierarchy, cache coherence and parallel computer architecture. He collaborates actively with the Grupo de Arquitectura de Computadores from the Universidad de Zaragoza (gaZ).<\/p>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div><div id=\"pg-gb4152-69f241488ff62-1\"  class=\"panel-grid panel-has-style\" ><div class=\"panel-row-style panel-row-style-for-gb4152-69f241488ff62-1\" ><div id=\"pgc-gb4152-69f241488ff62-1-0\"  class=\"panel-grid-cell\" ><div id=\"panel-gb4152-69f241488ff62-1-0-0\" class=\"so-panel widget widget_sow-headline panel-first-child\" data-index=\"2\" ><div\n\t\t\t\n\t\t\tclass=\"so-widget-sow-headline so-widget-sow-headline-default-244eb6bef45a-4152\"\n\t\t\t\n\t\t><div class=\"sow-headline-container\">\n\t\t\t\t\t\t\t<h5 class=\"sow-headline\">\n\t\t\t\t\t\tPUBLICATIONS\t\t\t\t\t\t<\/h5>\n\t\t\t\t\t\t\t\t\t\t\t<div class=\"decoration\">\n\t\t\t\t\t\t<div class=\"decoration-inside\"><\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n<\/div><\/div><div id=\"panel-gb4152-69f241488ff62-1-0-1\" class=\"so-panel widget widget_sow-editor panel-last-child\" data-index=\"3\" ><div\n\t\t\t\n\t\t\tclass=\"so-widget-sow-editor so-widget-sow-editor-base\"\n\t\t\t\n\t\t>\n<div class=\"siteorigin-widget-tinymce textwidget\">\n\t<div class=\"teachpress_pub_list\"><form name=\"tppublistform\" method=\"get\" action=\"\"><a name=\"tppubs\" id=\"tppubs\"><\/a><div class=\"teachpress_filter\"><select class=\"default\" name=\"yr\" id=\"yr\" tabindex=\"2\" onchange=\"teachpress_jumpMenu('parent',this, 'https:\/\/gaz.i3a.es\/es\/victor-soria-pardos\/?')\">\r\n                   <option value=\"tgid=&amp;type=&amp;auth=&amp;usr=&amp;yr=#tppubs\">Todos los a\u00f1os<\/option>\r\n                   <option value = \"tgid=&amp;type=&amp;auth=&amp;usr=&amp;yr=2026#tppubs\" >2026<\/option><option value = \"tgid=&amp;type=&amp;auth=&amp;usr=&amp;yr=2025#tppubs\" >2025<\/option><option value = \"tgid=&amp;type=&amp;auth=&amp;usr=&amp;yr=2024#tppubs\" >2024<\/option><option value = \"tgid=&amp;type=&amp;auth=&amp;usr=&amp;yr=2023#tppubs\" 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href=\"https:\/\/gaz.i3a.es\/es\/victor-soria-pardos\/?limit=2&amp;tgid=&amp;yr=&amp;type=&amp;usr=&amp;auth=&amp;tsr=#tppubs\" title=\"p\u00e1gina siguiente\" class=\"page-numbers button\">&rsaquo;<\/a> <a href=\"https:\/\/gaz.i3a.es\/es\/victor-soria-pardos\/?limit=3&amp;tgid=&amp;yr=&amp;type=&amp;usr=&amp;auth=&amp;tsr=#tppubs\" title=\"\u00faltima p\u00e1gina\" class=\"page-numbers button\">&raquo;<\/a> <\/div><\/div><div class=\"teachpress_publication_list\"><h3 class=\"tp_h3\" id=\"tp_h3_2026\">2026<\/h3><h3 class=\"tp_h3\" id=\"tp_h3_inproceedings\">Proceedings Articles<\/h3><div class=\"tp_publication tp_publication_inproceedings\"><div class=\"tp_pub_info\"><p class=\"tp_pub_author\"> Siracusa, Marco;  Hsu, Olivia;  Soria-Pardos, Victor;  Randall, Joshua;  Grasset, Arnaud;  Biscondi, Eric;  Joseph, Doug;  Allen, Randy;  Kjolstad, Fredrik;  Planas, Miquel Moret\u00f3;  Armejach, Adri\u00e0<\/p><p class=\"tp_pub_title\"><a class=\"tp_title_link\" onclick=\"teachpress_pub_showhide('890','tp_links')\" style=\"cursor:pointer;\">Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures<\/a> <span class=\"tp_pub_type tp_  inproceedings\">Proceedings Article<\/span> <\/p><p class=\"tp_pub_additional\"><span class=\"tp_pub_additional_in\">En: <\/span><span class=\"tp_pub_additional_year\">2026<\/span>.<\/p><p class=\"tp_pub_menu\"><span class=\"tp_resource_link\"><a id=\"tp_links_sh_890\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('890','tp_links')\" title=\"Mostrar enlaces y recursos\" style=\"cursor:pointer;\">Enlaces<\/a><\/span> | <span class=\"tp_bibtex_link\"><a id=\"tp_bibtex_sh_890\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('890','tp_bibtex')\" title=\"Mostrar entrada BibTeX \" style=\"cursor:pointer;\">BibTeX<\/a><\/span><\/p><div class=\"tp_bibtex\" id=\"tp_bibtex_890\" style=\"display:none;\"><div class=\"tp_bibtex_entry\"><pre>@inproceedings{siracusa2025ember,<br \/>\r\ntitle = {Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures},<br \/>\r\nauthor = {Marco Siracusa and Olivia Hsu and Victor Soria-Pardos and Joshua Randall and Arnaud Grasset and Eric Biscondi and Doug Joseph and Randy Allen and Fredrik Kjolstad and Miquel Moret\u00f3 Planas and Adri\u00e0 Armejach},<br \/>\r\nurl = {https:\/\/arxiv.org\/pdf\/2504.09870},<br \/>\r\nyear  = {2026},<br \/>\r\ndate = {2026-01-01},<br \/>\r\nurldate = {2026-01-01},<br \/>\r\njournal = {Proceedings of the 22nd ACM International Symposium on Code Generation and Optimization, CGO },<br \/>\r\nkeywords = {},<br \/>\r\npubstate = {published},<br \/>\r\ntppubtype = {inproceedings}<br \/>\r\n}<br \/>\r\n<\/pre><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('890','tp_bibtex')\">Cerrar<\/a><\/p><\/div><div class=\"tp_links\" id=\"tp_links_890\" style=\"display:none;\"><div class=\"tp_links_entry\"><ul class=\"tp_pub_list\"><li><i class=\"ai ai-arxiv\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/arxiv.org\/pdf\/2504.09870\" title=\"https:\/\/arxiv.org\/pdf\/2504.09870\" target=\"_blank\">https:\/\/arxiv.org\/pdf\/2504.09870<\/a><\/li><\/ul><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('890','tp_links')\">Cerrar<\/a><\/p><\/div><\/div><\/div><h3 class=\"tp_h3\" id=\"tp_h3_2025\">2025<\/h3><h3 class=\"tp_h3\" id=\"tp_h3_inproceedings\">Proceedings Articles<\/h3><div class=\"tp_publication tp_publication_inproceedings\"><div class=\"tp_pub_info\"><p class=\"tp_pub_author\"> Soria-Pardos, V\u00edctor;  Armejach, Adri\u00e0;  Su\u00e1rez, Dar\u00edo;  Martinot, Didier;  Grasset, Arnaud;  Moret\u00f3, Miquel<\/p><p class=\"tp_pub_title\"><a class=\"tp_title_link\" onclick=\"teachpress_pub_showhide('895','tp_links')\" style=\"cursor:pointer;\">FLAMA: Architecting floating-point atomic memory operations for heterogeneous HPC systems<\/a> <span class=\"tp_pub_type tp_  inproceedings\">Proceedings Article<\/span> <\/p><p class=\"tp_pub_additional\"><span class=\"tp_pub_additional_in\">En: <\/span><span class=\"tp_pub_additional_booktitle\">2025 28th Euromicro Conference on Digital System Design (DSD), <\/span><span class=\"tp_pub_additional_pages\">pp. 435\u2013442, <\/span><span class=\"tp_pub_additional_organization\">IEEE <\/span><span class=\"tp_pub_additional_publisher\">IEEE, <\/span><span class=\"tp_pub_additional_year\">2025<\/span>.<\/p><p class=\"tp_pub_menu\"><span class=\"tp_abstract_link\"><a id=\"tp_abstract_sh_895\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('895','tp_abstract')\" title=\"Mostrar resumen\" style=\"cursor:pointer;\">Resumen<\/a><\/span> | <span class=\"tp_resource_link\"><a id=\"tp_links_sh_895\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('895','tp_links')\" title=\"Mostrar enlaces y recursos\" style=\"cursor:pointer;\">Enlaces<\/a><\/span> | <span class=\"tp_bibtex_link\"><a id=\"tp_bibtex_sh_895\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('895','tp_bibtex')\" title=\"Mostrar entrada BibTeX \" style=\"cursor:pointer;\">BibTeX<\/a><\/span><\/p><div class=\"tp_bibtex\" id=\"tp_bibtex_895\" style=\"display:none;\"><div class=\"tp_bibtex_entry\"><pre>@inproceedings{soria2025flama,<br \/>\r\ntitle = {FLAMA: Architecting floating-point atomic memory operations for heterogeneous HPC systems},<br \/>\r\nauthor = {V\u00edctor Soria-Pardos and Adri\u00e0 Armejach and Dar\u00edo Su\u00e1rez and Didier Martinot and Arnaud Grasset and Miquel Moret\u00f3},<br \/>\r\nurl = {https:\/\/upcommons.upc.edu\/server\/api\/core\/bitstreams\/9199c411-ce89-4327-a06b-bf21838aa8db\/content},<br \/>\r\ndoi = {10.1109\/DSD67783.2025.00066},<br \/>\r\nyear  = {2025},<br \/>\r\ndate = {2025-01-01},<br \/>\r\nurldate = {2025-01-01},<br \/>\r\nbooktitle = {2025 28th Euromicro Conference on Digital System Design (DSD)},<br \/>\r\npages = {435\u2013442},<br \/>\r\npublisher = {IEEE},<br \/>\r\norganization = {IEEE},<br \/>\r\nabstract = {Current heterogeneous systems integrate generalpurpose Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs). The efficient use of such systems requires a significant programming effort to distribute computation and synchronize across devices, which usually involves using Atomic Memory Operations (AMOs). Arm recently launched a floating-point Atomic Memory Operations (FAMOs) extension to perform atomic updates on floating-point data types specifically. This work characterizes and models heterogeneous architectures to understand how floating-point AMOs impact graph, Machine Learning (ML), and high-performance computing (HPC) workloads. Our analysis shows that many AMOs are performed on floating-point data, which modern systems execute using inefficient compare-and-swap (CAS) constructs. Therefore, replacing CASbased constructs with FAMOs can improve a wide range of workloads. Moreover, we analyze the trade-offs of executing FAMOs at different memory hierarchy levels, either in private caches (near) or remotely in shared caches (far). We have extended the widely used AMBA CHI protocol to evaluate such FAMO support on a simulated chiplet-based heterogeneous architecture. While near FAMOs achieve an average 1.34\u00d7 speed-up, far FAMOs reach an average 1.58\u00d7 speed-up. We conclude that FAMOs can bridge the gap between CPU architecture and accelerators and enabling synchronization in key application domains.},<br \/>\r\nkeywords = {},<br \/>\r\npubstate = {published},<br \/>\r\ntppubtype = {inproceedings}<br \/>\r\n}<br \/>\r\n<\/pre><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('895','tp_bibtex')\">Cerrar<\/a><\/p><\/div><div class=\"tp_abstract\" id=\"tp_abstract_895\" style=\"display:none;\"><div class=\"tp_abstract_entry\">Current heterogeneous systems integrate generalpurpose Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs). The efficient use of such systems requires a significant programming effort to distribute computation and synchronize across devices, which usually involves using Atomic Memory Operations (AMOs). Arm recently launched a floating-point Atomic Memory Operations (FAMOs) extension to perform atomic updates on floating-point data types specifically. This work characterizes and models heterogeneous architectures to understand how floating-point AMOs impact graph, Machine Learning (ML), and high-performance computing (HPC) workloads. Our analysis shows that many AMOs are performed on floating-point data, which modern systems execute using inefficient compare-and-swap (CAS) constructs. Therefore, replacing CASbased constructs with FAMOs can improve a wide range of workloads. Moreover, we analyze the trade-offs of executing FAMOs at different memory hierarchy levels, either in private caches (near) or remotely in shared caches (far). We have extended the widely used AMBA CHI protocol to evaluate such FAMO support on a simulated chiplet-based heterogeneous architecture. While near FAMOs achieve an average 1.34\u00d7 speed-up, far FAMOs reach an average 1.58\u00d7 speed-up. We conclude that FAMOs can bridge the gap between CPU architecture and accelerators and enabling synchronization in key application domains.<\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('895','tp_abstract')\">Cerrar<\/a><\/p><\/div><div class=\"tp_links\" id=\"tp_links_895\" style=\"display:none;\"><div class=\"tp_links_entry\"><ul class=\"tp_pub_list\"><li><i class=\"fas fa-globe\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/upcommons.upc.edu\/server\/api\/core\/bitstreams\/9199c411-ce89-4327-a06b-bf21838aa8db\/content\" title=\"https:\/\/upcommons.upc.edu\/server\/api\/core\/bitstreams\/9199c411-ce89-4327-a06b-bf2[...]\" target=\"_blank\">https:\/\/upcommons.upc.edu\/server\/api\/core\/bitstreams\/9199c411-ce89-4327-a06b-bf2[&#8230;]<\/a><\/li><li><i class=\"ai ai-doi\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/dx.doi.org\/10.1109\/DSD67783.2025.00066\" title=\"DOI de seguimiento:10.1109\/DSD67783.2025.00066\" target=\"_blank\">doi:10.1109\/DSD67783.2025.00066<\/a><\/li><\/ul><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('895','tp_links')\">Cerrar<\/a><\/p><\/div><\/div><\/div><div class=\"tp_publication tp_publication_inproceedings\"><div class=\"tp_pub_info\"><p class=\"tp_pub_author\"> Soria-Pardos, V\u00edctor;  Armejach, Adri\u00e0;  M\u00fcck, Tiago;  Gracia, Dar\u00edo Su\u00e1rez;  Joao, Jose;  Moret\u00f3, Miquel<\/p><p class=\"tp_pub_title\"><a class=\"tp_title_link\" onclick=\"teachpress_pub_showhide('892','tp_links')\" style=\"cursor:pointer;\">Delegato: Locality-Aware Atomic Memory Operations on Chiplets<\/a> <span class=\"tp_pub_type tp_  inproceedings\">Proceedings Article<\/span> <\/p><p class=\"tp_pub_additional\"><span class=\"tp_pub_additional_in\">En: <\/span><span class=\"tp_pub_additional_booktitle\">Proceedings of the 58th IEEE\/ACM International Symposium on Microarchitecture, <\/span><span class=\"tp_pub_additional_pages\">pp. 1793\u20131808, <\/span><span class=\"tp_pub_additional_publisher\">ACM, <\/span><span class=\"tp_pub_additional_year\">2025<\/span>.<\/p><p class=\"tp_pub_menu\"><span class=\"tp_abstract_link\"><a id=\"tp_abstract_sh_892\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('892','tp_abstract')\" title=\"Mostrar resumen\" style=\"cursor:pointer;\">Resumen<\/a><\/span> | <span class=\"tp_resource_link\"><a id=\"tp_links_sh_892\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('892','tp_links')\" title=\"Mostrar enlaces y recursos\" style=\"cursor:pointer;\">Enlaces<\/a><\/span> | <span class=\"tp_bibtex_link\"><a id=\"tp_bibtex_sh_892\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('892','tp_bibtex')\" title=\"Mostrar entrada BibTeX \" style=\"cursor:pointer;\">BibTeX<\/a><\/span><\/p><div class=\"tp_bibtex\" id=\"tp_bibtex_892\" style=\"display:none;\"><div class=\"tp_bibtex_entry\"><pre>@inproceedings{soria2025delegato,<br \/>\r\ntitle = {Delegato: Locality-Aware Atomic Memory Operations on Chiplets},<br \/>\r\nauthor = {V\u00edctor Soria-Pardos and Adri\u00e0 Armejach and Tiago M\u00fcck and Dar\u00edo Su\u00e1rez Gracia and Jose Joao and Miquel Moret\u00f3},<br \/>\r\nurl = {https:\/\/dl.acm.org\/doi\/full\/10.1145\/3725843.3756030},<br \/>\r\ndoi = {10.1145\/3725843.375603},<br \/>\r\nyear  = {2025},<br \/>\r\ndate = {2025-01-01},<br \/>\r\nurldate = {2025-01-01},<br \/>\r\nbooktitle = {Proceedings of the 58th IEEE\/ACM International Symposium on Microarchitecture},<br \/>\r\npages = {1793\u20131808},<br \/>\r\npublisher = {ACM},<br \/>\r\nabstract = {The irruption of chiplet-based architectures has been a game changer, enabling higher transistor integration and core counts in a single socket. However, chiplets impose higher and non-uniform memory access (NUMA) latencies than monolithic integration. This harms the efficiency of atomic memory operations (AMOs), which are fundamental to implementing fine-grained synchronization and concurrent data structures on large systems. AMOs are executed either near the core (near) or at a remote location within the cache hierarchy (far). On near AMOs, the core\u2019s private cache fetches the target cache line in exclusiveness to modify it locally. Near AMOs cause significant data movement between private caches, especially harming parallel applications\u2019 performance on chiplet-based architectures. Alternatively, far AMOs can alleviate the communication overhead by reducing data movement between processing elements. However, current multicore architectures only support one type of far AMO, which sends all updates to a single serialization point (centralized AMOs).<br \/>\r\nThis work introduces two new types of far AMOs, delegated and migrating, that execute AMOs remotely without centralizing updates in a single point of the cache hierarchy. Combining centralized, delegated, and migrating AMOs allows the directory to select the best location to execute AMOs. Moreover, we propose Delegato, a tracing optimization to effectively transport usage information from private caches to the directory to predict the best atomic type to issue accurately. Additionally, we design a simple predictor on top of Delegato that seamlessly selects the best placement to perform AMOs based on the data access pattern and usage activity of cores. Our evaluation using gem5 shows that Delegato can speed up applications on average by 1.07 \u00d7 over centralized AMOs and by 1.13 \u00d7 over the state-of-the-art AMO predictor.},<br \/>\r\nkeywords = {},<br \/>\r\npubstate = {published},<br \/>\r\ntppubtype = {inproceedings}<br \/>\r\n}<br \/>\r\n<\/pre><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('892','tp_bibtex')\">Cerrar<\/a><\/p><\/div><div class=\"tp_abstract\" id=\"tp_abstract_892\" style=\"display:none;\"><div class=\"tp_abstract_entry\">The irruption of chiplet-based architectures has been a game changer, enabling higher transistor integration and core counts in a single socket. However, chiplets impose higher and non-uniform memory access (NUMA) latencies than monolithic integration. This harms the efficiency of atomic memory operations (AMOs), which are fundamental to implementing fine-grained synchronization and concurrent data structures on large systems. AMOs are executed either near the core (near) or at a remote location within the cache hierarchy (far). On near AMOs, the core\u2019s private cache fetches the target cache line in exclusiveness to modify it locally. Near AMOs cause significant data movement between private caches, especially harming parallel applications\u2019 performance on chiplet-based architectures. Alternatively, far AMOs can alleviate the communication overhead by reducing data movement between processing elements. However, current multicore architectures only support one type of far AMO, which sends all updates to a single serialization point (centralized AMOs).<br \/>\r\nThis work introduces two new types of far AMOs, delegated and migrating, that execute AMOs remotely without centralizing updates in a single point of the cache hierarchy. Combining centralized, delegated, and migrating AMOs allows the directory to select the best location to execute AMOs. Moreover, we propose Delegato, a tracing optimization to effectively transport usage information from private caches to the directory to predict the best atomic type to issue accurately. Additionally, we design a simple predictor on top of Delegato that seamlessly selects the best placement to perform AMOs based on the data access pattern and usage activity of cores. Our evaluation using gem5 shows that Delegato can speed up applications on average by 1.07 \u00d7 over centralized AMOs and by 1.13 \u00d7 over the state-of-the-art AMO predictor.<\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('892','tp_abstract')\">Cerrar<\/a><\/p><\/div><div class=\"tp_links\" id=\"tp_links_892\" style=\"display:none;\"><div class=\"tp_links_entry\"><ul class=\"tp_pub_list\"><li><i class=\"fas fa-globe\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/dl.acm.org\/doi\/full\/10.1145\/3725843.3756030\" title=\"https:\/\/dl.acm.org\/doi\/full\/10.1145\/3725843.3756030\" target=\"_blank\">https:\/\/dl.acm.org\/doi\/full\/10.1145\/3725843.3756030<\/a><\/li><li><i class=\"ai ai-doi\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/dx.doi.org\/10.1145\/3725843.375603\" title=\"DOI de seguimiento:10.1145\/3725843.375603\" target=\"_blank\">doi:10.1145\/3725843.375603<\/a><\/li><\/ul><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('892','tp_links')\">Cerrar<\/a><\/p><\/div><\/div><\/div><h3 class=\"tp_h3\" id=\"tp_h3_2024\">2024<\/h3><h3 class=\"tp_h3\" id=\"tp_h3_article\">Art\u00edculos de revista<\/h3><div class=\"tp_publication tp_publication_article\"><div class=\"tp_pub_info\"><p class=\"tp_pub_author\"> L\u00f3pez-Villellas, Lori\u00e9n;  Langarita-Ben\u00edtez, Rub\u00e9n;  Badouh, Asaf;  Soria-Pardos, V\u00edctor;  Aguado-Puig, Quim;  L\u00f3pez-Parad\u00eds, Guillem;  Doblas, Max;  Setoain, Javier;  Kim, Chulho;  Ono, Makoto;  Armejach, Adri\u00e0;  Marco-Sola, Santiago;  Alastruey-Bened\u00e9, Jes\u00fas;  Ib\u00e1\u00f1ez, Pablo;  Moret\u00f3, Miquel<\/p><p class=\"tp_pub_title\"><a class=\"tp_title_link\" onclick=\"teachpress_pub_showhide('844','tp_links')\" style=\"cursor:pointer;\">GenArchBench: A genomics benchmark suite for arm HPC processors<\/a> <span class=\"tp_pub_type tp_  article\">Art\u00edculo de revista<\/span> <\/p><p class=\"tp_pub_additional\"><span class=\"tp_pub_additional_in\">En: <\/span><span class=\"tp_pub_additional_journal\">Future Generation Computer Systems, <\/span><span class=\"tp_pub_additional_volume\">vol. 157, <\/span><span class=\"tp_pub_additional_pages\">pp. 313-329, <\/span><span class=\"tp_pub_additional_year\">2024<\/span>, <span class=\"tp_pub_additional_issn\">ISSN: 0167-739X<\/span>.<\/p><p class=\"tp_pub_menu\"><span class=\"tp_abstract_link\"><a id=\"tp_abstract_sh_844\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('844','tp_abstract')\" title=\"Mostrar resumen\" style=\"cursor:pointer;\">Resumen<\/a><\/span> | <span class=\"tp_resource_link\"><a id=\"tp_links_sh_844\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('844','tp_links')\" title=\"Mostrar enlaces y recursos\" style=\"cursor:pointer;\">Enlaces<\/a><\/span> | <span class=\"tp_bibtex_link\"><a id=\"tp_bibtex_sh_844\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('844','tp_bibtex')\" title=\"Mostrar entrada BibTeX \" style=\"cursor:pointer;\">BibTeX<\/a><\/span><\/p><div class=\"tp_bibtex\" id=\"tp_bibtex_844\" style=\"display:none;\"><div class=\"tp_bibtex_entry\"><pre>@article{LOPEZVILLELLAS2024313,<br \/>\r\ntitle = {GenArchBench: A genomics benchmark suite for arm HPC processors},<br \/>\r\nauthor = {Lori\u00e9n L\u00f3pez-Villellas and Rub\u00e9n Langarita-Ben\u00edtez and Asaf Badouh and V\u00edctor Soria-Pardos and Quim Aguado-Puig and Guillem L\u00f3pez-Parad\u00eds and Max Doblas and Javier Setoain and Chulho Kim and Makoto Ono and Adri\u00e0 Armejach and Santiago Marco-Sola and Jes\u00fas Alastruey-Bened\u00e9 and Pablo Ib\u00e1\u00f1ez and Miquel Moret\u00f3},<br \/>\r\nurl = {https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0167739X24001250},<br \/>\r\ndoi = {https:\/\/doi.org\/10.1016\/j.future.2024.03.050},<br \/>\r\nissn = {0167-739X},<br \/>\r\nyear  = {2024},<br \/>\r\ndate = {2024-01-01},<br \/>\r\njournal = {Future Generation Computer Systems},<br \/>\r\nvolume = {157},<br \/>\r\npages = {313-329},<br \/>\r\nabstract = {Arm usage has substantially grown in the High-Performance Computing (HPC) community. Japanese supercomputer Fugaku, powered by Arm-based A64FX processors, held the top position on the Top500 list between June 2020 and June 2022, currently sitting in the fourth position. The recently released 7th generation of Amazon EC2 instances for compute-intensive workloads (C7 g) is also powered by Arm Graviton3 processors. Projects like European Mont-Blanc and U.S. DOE\/NNSA Astra are further examples of Arm irruption in HPC. In parallel, over the last decade, the rapid improvement of genomic sequencing technologies and the exponential growth of sequencing data has placed a significant bottleneck on the computational side. While most genomics applications have been thoroughly tested and optimized for x86 systems, just a few are prepared to perform efficiently on Arm machines. Moreover, these applications do not exploit the newly introduced Scalable Vector Extensions (SVE). This paper presents GenArchBench, the first genome analysis benchmark suite targeting Arm architectures. We have selected computationally demanding kernels from the most widely used tools in genome data analysis and ported them to Arm-based A64FX and Graviton3 processors. Overall, the GenArch benchmark suite comprises 13 multi-core kernels from critical stages of widely-used genome analysis pipelines, including base-calling, read mapping, variant calling, and genome assembly. Our benchmark suite includes different input data sets per kernel (small and large), each with a corresponding regression test to verify the correctness of each execution automatically. Moreover, the porting features the usage of the novel Arm SVE instructions, algorithmic and code optimizations, and the exploitation of Arm-optimized libraries. We present the optimizations implemented in each kernel and a detailed performance evaluation and comparison of their performance on four different HPC machines (i.e., A64FX, Graviton3, Intel Xeon Skylake Platinum, and AMD EPYC Rome). Overall, the experimental evaluation shows that Graviton3 outperforms other machines on average. Moreover, we observed that the performance of the A64FX is significantly constrained by its small memory hierarchy and latencies. Additionally, as proof of concept, we study the performance of a production-ready tool that exploits two of the ported and optimized genomic kernels.},<br \/>\r\nkeywords = {},<br \/>\r\npubstate = {published},<br \/>\r\ntppubtype = {article}<br \/>\r\n}<br \/>\r\n<\/pre><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('844','tp_bibtex')\">Cerrar<\/a><\/p><\/div><div class=\"tp_abstract\" id=\"tp_abstract_844\" style=\"display:none;\"><div class=\"tp_abstract_entry\">Arm usage has substantially grown in the High-Performance Computing (HPC) community. Japanese supercomputer Fugaku, powered by Arm-based A64FX processors, held the top position on the Top500 list between June 2020 and June 2022, currently sitting in the fourth position. The recently released 7th generation of Amazon EC2 instances for compute-intensive workloads (C7 g) is also powered by Arm Graviton3 processors. Projects like European Mont-Blanc and U.S. DOE\/NNSA Astra are further examples of Arm irruption in HPC. In parallel, over the last decade, the rapid improvement of genomic sequencing technologies and the exponential growth of sequencing data has placed a significant bottleneck on the computational side. While most genomics applications have been thoroughly tested and optimized for x86 systems, just a few are prepared to perform efficiently on Arm machines. Moreover, these applications do not exploit the newly introduced Scalable Vector Extensions (SVE). This paper presents GenArchBench, the first genome analysis benchmark suite targeting Arm architectures. We have selected computationally demanding kernels from the most widely used tools in genome data analysis and ported them to Arm-based A64FX and Graviton3 processors. Overall, the GenArch benchmark suite comprises 13 multi-core kernels from critical stages of widely-used genome analysis pipelines, including base-calling, read mapping, variant calling, and genome assembly. Our benchmark suite includes different input data sets per kernel (small and large), each with a corresponding regression test to verify the correctness of each execution automatically. Moreover, the porting features the usage of the novel Arm SVE instructions, algorithmic and code optimizations, and the exploitation of Arm-optimized libraries. We present the optimizations implemented in each kernel and a detailed performance evaluation and comparison of their performance on four different HPC machines (i.e., A64FX, Graviton3, Intel Xeon Skylake Platinum, and AMD EPYC Rome). Overall, the experimental evaluation shows that Graviton3 outperforms other machines on average. Moreover, we observed that the performance of the A64FX is significantly constrained by its small memory hierarchy and latencies. Additionally, as proof of concept, we study the performance of a production-ready tool that exploits two of the ported and optimized genomic kernels.<\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('844','tp_abstract')\">Cerrar<\/a><\/p><\/div><div class=\"tp_links\" id=\"tp_links_844\" style=\"display:none;\"><div class=\"tp_links_entry\"><ul class=\"tp_pub_list\"><li><i class=\"fas fa-globe\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0167739X24001250\" title=\"https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0167739X24001250\" target=\"_blank\">https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0167739X24001250<\/a><\/li><li><i class=\"ai ai-doi\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/dx.doi.org\/https:\/\/doi.org\/10.1016\/j.future.2024.03.050\" title=\"DOI de seguimiento:https:\/\/doi.org\/10.1016\/j.future.2024.03.050\" target=\"_blank\">doi:https:\/\/doi.org\/10.1016\/j.future.2024.03.050<\/a><\/li><\/ul><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('844','tp_links')\">Cerrar<\/a><\/p><\/div><\/div><\/div><h3 class=\"tp_h3\" id=\"tp_h3_2023\">2023<\/h3><h3 class=\"tp_h3\" id=\"tp_h3_inproceedings\">Proceedings Articles<\/h3><div class=\"tp_publication tp_publication_inproceedings\"><div class=\"tp_pub_info\"><p class=\"tp_pub_author\"> Soria-Pardos, V\u00edctor;  Armejach, Adria;  M\u00fcck, Tiago;  Su\u00e1rez-Gracia, Dario;  Joao, Jos\u00e9;  Rico, Alejandro;  Moret\u00f3, Miquel<\/p><p class=\"tp_pub_title\"><a class=\"tp_title_link\" onclick=\"teachpress_pub_showhide('888','tp_links')\" style=\"cursor:pointer;\">DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations<\/a> <span class=\"tp_pub_type tp_  inproceedings\">Proceedings Article<\/span> <\/p><p class=\"tp_pub_additional\"><span class=\"tp_pub_additional_in\">En: <\/span><span class=\"tp_pub_additional_booktitle\">Proceedings of the 50th Annual International Symposium on Computer Architecture, <\/span><span class=\"tp_pub_additional_pages\">pp. 1\u201313, <\/span><span class=\"tp_pub_additional_publisher\">ACM, <\/span><span class=\"tp_pub_additional_year\">2023<\/span>.<\/p><p class=\"tp_pub_menu\"><span class=\"tp_abstract_link\"><a id=\"tp_abstract_sh_888\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('888','tp_abstract')\" title=\"Mostrar resumen\" style=\"cursor:pointer;\">Resumen<\/a><\/span> | <span class=\"tp_resource_link\"><a id=\"tp_links_sh_888\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('888','tp_links')\" title=\"Mostrar enlaces y recursos\" style=\"cursor:pointer;\">Enlaces<\/a><\/span> | <span class=\"tp_bibtex_link\"><a id=\"tp_bibtex_sh_888\" class=\"tp_show\" onclick=\"teachpress_pub_showhide('888','tp_bibtex')\" title=\"Mostrar entrada BibTeX \" style=\"cursor:pointer;\">BibTeX<\/a><\/span><\/p><div class=\"tp_bibtex\" id=\"tp_bibtex_888\" style=\"display:none;\"><div class=\"tp_bibtex_entry\"><pre>@inproceedings{soria2023dynamo,<br \/>\r\ntitle = {DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations},<br \/>\r\nauthor = {V\u00edctor Soria-Pardos and Adria Armejach and Tiago M\u00fcck and Dario Su\u00e1rez-Gracia and Jos\u00e9 Joao and Alejandro Rico and Miquel Moret\u00f3},<br \/>\r\nurl = {https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3579371.3589065},<br \/>\r\ndoi = {10.1145\/3579371.3589065},<br \/>\r\nyear  = {2023},<br \/>\r\ndate = {2023-01-01},<br \/>\r\nurldate = {2023-01-01},<br \/>\r\nbooktitle = {Proceedings of the 50th Annual International Symposium on Computer Architecture},<br \/>\r\npages = {1\u201313},<br \/>\r\npublisher = {ACM},<br \/>\r\nabstract = {With increasing core counts in modern multi-core designs, the overhead of synchronization jeopardizes the scalability and efficiency of parallel applications. To mitigate these overheads, modern cache-coherent protocols offer support for Atomic Memory Operations (AMOs) that can be executed near-core (near) or remotely in the on-chip memory hierarchy (far).<br \/>\r\nThis paper evaluates current available static AMO execution policies implemented in multi-core Systems-on-Chip (SoC) designs, which select AMOs&#039; execution placement (near or far) based on the cache block coherence state. We propose three static policies and show that the performance of static policies is application dependent. Moreover, we show that one of our proposed static policies outperforms currently available implementations.<br \/>\r\nFurthermore, we propose DynAMO, a predictor that selects the best location to execute the AMOs. DynAMO identifies the different locality patterns to make informed decisions, improving AMO latency and increasing overall throughput. DynAMO outperforms the best-performing static policy and provides geometric mean speed-ups of 1.09\u00d7 across all workloads and 1.31\u00d7 on AMO-intensive applications with respect to executing all AMOs near.},<br \/>\r\nkeywords = {},<br \/>\r\npubstate = {published},<br \/>\r\ntppubtype = {inproceedings}<br \/>\r\n}<br \/>\r\n<\/pre><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('888','tp_bibtex')\">Cerrar<\/a><\/p><\/div><div class=\"tp_abstract\" id=\"tp_abstract_888\" style=\"display:none;\"><div class=\"tp_abstract_entry\">With increasing core counts in modern multi-core designs, the overhead of synchronization jeopardizes the scalability and efficiency of parallel applications. To mitigate these overheads, modern cache-coherent protocols offer support for Atomic Memory Operations (AMOs) that can be executed near-core (near) or remotely in the on-chip memory hierarchy (far).<br \/>\r\nThis paper evaluates current available static AMO execution policies implemented in multi-core Systems-on-Chip (SoC) designs, which select AMOs&#039; execution placement (near or far) based on the cache block coherence state. We propose three static policies and show that the performance of static policies is application dependent. Moreover, we show that one of our proposed static policies outperforms currently available implementations.<br \/>\r\nFurthermore, we propose DynAMO, a predictor that selects the best location to execute the AMOs. DynAMO identifies the different locality patterns to make informed decisions, improving AMO latency and increasing overall throughput. DynAMO outperforms the best-performing static policy and provides geometric mean speed-ups of 1.09\u00d7 across all workloads and 1.31\u00d7 on AMO-intensive applications with respect to executing all AMOs near.<\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('888','tp_abstract')\">Cerrar<\/a><\/p><\/div><div class=\"tp_links\" id=\"tp_links_888\" style=\"display:none;\"><div class=\"tp_links_entry\"><ul class=\"tp_pub_list\"><li><i class=\"fas fa-globe\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3579371.3589065\" title=\"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3579371.3589065\" target=\"_blank\">https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3579371.3589065<\/a><\/li><li><i class=\"ai ai-doi\"><\/i><a class=\"tp_pub_list\" href=\"https:\/\/dx.doi.org\/10.1145\/3579371.3589065\" title=\"DOI de seguimiento:10.1145\/3579371.3589065\" target=\"_blank\">doi:10.1145\/3579371.3589065<\/a><\/li><\/ul><\/div><p class=\"tp_close_menu\"><a class=\"tp_close\" onclick=\"teachpress_pub_showhide('888','tp_links')\">Cerrar<\/a><\/p><\/div><\/div><\/div><\/div><div class=\"tablenav\"><div class=\"tablenav-pages\"><span class=\"displaying-num\">12 registros<\/span> <a class=\"page-numbers button disabled\">&laquo;<\/a> <a class=\"page-numbers button disabled\">&lsaquo;<\/a> 1 de 3 <a href=\"https:\/\/gaz.i3a.es\/es\/victor-soria-pardos\/?limit=2&amp;tgid=&amp;yr=&amp;type=&amp;usr=&amp;auth=&amp;tsr=#tppubs\" title=\"p\u00e1gina siguiente\" class=\"page-numbers button\">&rsaquo;<\/a> <a href=\"https:\/\/gaz.i3a.es\/es\/victor-soria-pardos\/?limit=3&amp;tgid=&amp;yr=&amp;type=&amp;usr=&amp;auth=&amp;tsr=#tppubs\" title=\"\u00faltima p\u00e1gina\" class=\"page-numbers button\">&raquo;<\/a> <\/div><\/div><\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div><\/div>\n\n\n<p><\/p>","protected":false},"excerpt":{"rendered":"","protected":false},"author":3,"featured_media":3600,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[242,239],"tags":[],"class_list":["post-4152","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-collaborators","category-team"],"_links":{"self":[{"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/posts\/4152","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/comments?post=4152"}],"version-history":[{"count":6,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/posts\/4152\/revisions"}],"predecessor-version":[{"id":4161,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/posts\/4152\/revisions\/4161"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/media\/3600"}],"wp:attachment":[{"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/media?parent=4152"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/categories?post=4152"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/gaz.i3a.es\/es\/wp-json\/wp\/v2\/tags?post=4152"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}