Email: alvabre@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Alejandro Valero received the PhD degree in Computer Engineering from the Universitat Politècnica de València, Spain, in 2013. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston, MA, USA, and the University of Cambridge, UK. Since 2016, he has been a Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain, where he teaches several courses on computer organization, including Introduction to Computer Systems, Operating Systems, Data Center Design, and Programming and Architecture of Heterogeneous Computing Systems. His PhD research contributions to the design of high-performance and energy-efficient CPU on-chip memory hierarchies were recognized with the Intel Doctoral Student Honor Program Award and the ACM Student Research Competition Award in 2012 and 2013, respectively. His current research interests mainly focus on emerging memory technologies and the design of GPU and ASIC architectures in terms of performance, energy efficiency, and reliability. Dr. Valero has participated in several national and local funded projects, and has published in the main venues of his area, including the International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), the International Conference on Supercomputing (ICS), IEEE Transactions on Computers, and IEEE Transactions on VLSI Systems. He has served as Program Committee Member and Referee in a significant number of conferences, journals, and workshops. Dr. Valero is a member of the Aragon Institute of Engineering Research (I3A) and the HiPEAC European NoE.
PUBLICATIONS
2018
Journal Articles
Valero, Alejandro; Candel, Francisco; Suarez-Gracia, Dario; Petit, Salvador; Sahuquillo, Julio
An Aging-Aware GPU Register File Design Based on Data Redundancy Journal Article
In: IEEE Transactions on Computers, vol. 68, no. 1, pp. 4–20, 2018.
@article{valero2018aging,
title = {An Aging-Aware GPU Register File Design Based on Data Redundancy},
author = {Alejandro Valero and Francisco Candel and Dario Suarez-Gracia and Salvador Petit and Julio Sahuquillo},
year = {2018},
date = {2018-01-01},
journal = {IEEE Transactions on Computers},
volume = {68},
number = {1},
pages = {4--20},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Candel, Francisco; Petit, Salvador; Valero, Alejandro; Sahuquillo, Julio
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache Proceedings Article
In: European Conference on Parallel Processing, pp. 235–248, Springer 2018.
@inproceedings{candel2018improving,
title = {Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache},
author = {Francisco Candel and Salvador Petit and Alejandro Valero and Julio Sahuquillo},
year = {2018},
date = {2018-01-01},
booktitle = {European Conference on Parallel Processing},
pages = {235--248},
organization = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2017
Proceedings Articles
Candel, Francisco; Valero, Alejandro; Petit, Salvador; Suárez-Gracia, Darío; Sahuquillo, Julio
Exploiting data compression to mitigate aging in GPU register files Proceedings Article
In: 2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 57–64, IEEE 2017.
@inproceedings{candel2017exploiting,
title = {Exploiting data compression to mitigate aging in GPU register files},
author = {Francisco Candel and Alejandro Valero and Salvador Petit and Darío Suárez-Gracia and Julio Sahuquillo},
year = {2017},
date = {2017-01-01},
booktitle = {2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)},
pages = {57--64},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2016
Journal Articles
Valero, Alejandro; Miralaei, Negar; Petit, Salvador; Sahuquillo, Julio; Jones, Timothy M
On microarchitectural mechanisms for cache wearout reduction Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 857–871, 2016.
@article{valero2016microarchitectural,
title = {On microarchitectural mechanisms for cache wearout reduction},
author = {Alejandro Valero and Negar Miralaei and Salvador Petit and Julio Sahuquillo and Timothy M Jones},
year = {2016},
date = {2016-01-01},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume = {25},
number = {3},
pages = {857--871},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2015
Journal Articles
Valero, Alejandro; Miralaei, Negar; Petit, Salvador; Sahuquillo, Julio; Jones, Timothy M
Enhancing the L1 data cache design to mitigate HCI Journal Article
In: IEEE Computer Architecture Letters, vol. 15, no. 2, pp. 93–96, 2015.
@article{valero2015enhancing,
title = {Enhancing the L1 data cache design to mitigate HCI},
author = {Alejandro Valero and Negar Miralaei and Salvador Petit and Julio Sahuquillo and Timothy M Jones},
year = {2015},
date = {2015-01-01},
journal = {IEEE Computer Architecture Letters},
volume = {15},
number = {2},
pages = {93--96},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}