Javier Resano Ezcaray
University of Zaragoza
I received the Bachelor Degree in Physics in 1997, a Master Degree in Computer Science in 1999, and the PhD degree in Computer architecture in 2005 at the Universidad Complutense of Madrid, Spain. I worked eight years as Assistant and Associate Professor at this University, and collaborated with the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium.
Currently I am Associate Professor at the Computer Eng. Department of the Universidad de Zaragoza (Spain), and a member of the Gaz research group (Computer Architecture group from Universidad of Zaragoza) and the Aragón Institute for Engineering Research (I3A).
My research has been focused in hardware/software co-design, task scheduling techniques for multi-processor systems, Digital Logic design using FPGAs, dynamically reconfigurable hardware and efficient accelerators for machine learning and remote sensing.
FPGA Accelerator for Gradient Boosting Decision Trees Journal Article
In: Electronics, vol. 10, no. 3, pp. 314, 2021.
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 1993–2003, 2020.
Inference in supervised spectral classifiers for on-board hyperspectral imaging: An overview Journal Article
In: Remote Sensing, vol. 12, no. 3, pp. 534, 2020.
GPU-Friendly Neural Networks for Remote Sensing Scene Classification Journal Article
In: IEEE Geoscience and Remote Sensing Letters, 2020.
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array Journal Article
In: IET Computers & Digital Techniques, vol. 12, no. 4, pp. 150–157, 2018.