Senior Lecturer
Email: rgran@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Rubén Gran Tejero graduated in Computer Science from the University of Zaragoza, Spain. He received his Ph.D. from the Polytechnic University of Catalonia (UPC), Spain, in 2010. Since 2010, he has been an Associate Professor at the Department of Computer Science and Systems Engineering, University of Zaragoza. His research interests include hard real-time systems, hardware for reducing worst-case execution time and energy consumption, efficient processor microarchitecture, and effective programming for parallel and heterogeneous systems. Dr. Gran Tejero is member of the Aragon Institute of Engineering Research (I3A) and the Spanish Society of Computer Architecture (SARTECO).
PUBLICATIONS
2019
Journal Articles
Guzman, Maria Angelica Davila; Nozal, Raúl; Tejero, Rubén Gran; Villarroya-Gaudó, María; Gracia, Darío Suárez; Bosque, Jose Luis
Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL Journal Article
In: The Journal of Supercomputing, vol. 75, no. 3, pp. 1732–1746, 2019.
@article{guzman2019cooperative,
title = {Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL},
author = {Maria Angelica Davila Guzman and Raúl Nozal and Rubén Gran Tejero and María Villarroya-Gaudó and Darío Suárez Gracia and Jose Luis Bosque},
year = {2019},
date = {2019-01-01},
journal = {The Journal of Supercomputing},
volume = {75},
number = {3},
pages = {1732--1746},
publisher = {Springer US},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Nunez-Yanez, Jose; Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Suarez, Dario; Gran, Ruben
Simultaneous multiprocessing in a software-defined heterogeneous FPGA Journal Article
In: The Journal of Supercomputing, vol. 75, no. 8, pp. 4078–4095, 2019.
@article{nunez2019simultaneous,
title = {Simultaneous multiprocessing in a software-defined heterogeneous FPGA},
author = {Jose Nunez-Yanez and Sam Amiri and Mohammad Hosseinabady and Andrés Rodríguez and Rafael Asenjo and Angeles Navarro and Dario Suarez and Ruben Gran},
year = {2019},
date = {2019-01-01},
journal = {The Journal of Supercomputing},
volume = {75},
number = {8},
pages = {4078--4095},
publisher = {Springer US},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Rodríguez, Andrés; Navarro, Angeles; Asenjo, Rafael; Corbera, Francisco; Gran, Rubén; Suárez, Darío; Nunez-Yanez, Jose
Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform Journal Article
In: The Journal of Supercomputing, pp. 1–21, 2019.
@article{rodriguez2019parallel,
title = {Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform},
author = {Andrés Rodríguez and Angeles Navarro and Rafael Asenjo and Francisco Corbera and Rubén Gran and Darío Suárez and Jose Nunez-Yanez},
year = {2019},
date = {2019-01-01},
journal = {The Journal of Supercomputing},
pages = {1--21},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Rodríguez, Andrés; Navarro, Angeles; Asenjo, Rafael; Corbera, Francisco; Gran, Rubén; Suárez, Darío; Nunez-Yanez, Jose
Exploring Heterogeneous Scheduling for Edge Computing with CPU and FPGA MPSoCs Journal Article
In: Journal of Systems Architecture, 2019.
@article{rodriguez2019exploring,
title = {Exploring Heterogeneous Scheduling for Edge Computing with CPU and FPGA MPSoCs},
author = {Andrés Rodríguez and Angeles Navarro and Rafael Asenjo and Francisco Corbera and Rubén Gran and Darío Suárez and Jose Nunez-Yanez},
year = {2019},
date = {2019-01-01},
journal = {Journal of Systems Architecture},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Valero, Alejandro; Gracia, Darío Suárez; Tejero, Ruben Gran; Ramos, Luis M; Navarro-Torres, Agustín; Muñoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Murillo, Ana C; Montijano, Eduardo; others,
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer Proceedings Article
In: Proceedings of the Workshop on Computer Architecture Education, pp. 1–8, 2019.
@inproceedings{valero2019exposing,
title = {Exposing Abstraction-Level Interactions with a Parallel Ray Tracer},
author = {Alejandro Valero and Darío Suárez Gracia and Ruben Gran Tejero and Luis M Ramos and Agustín Navarro-Torres and Adolfo Muñoz and Joaquín Ezpeleta and José Luis Briz and Ana C Murillo and Eduardo Montijano and others},
year = {2019},
date = {2019-01-01},
booktitle = {Proceedings of the Workshop on Computer Architecture Education},
pages = {1--8},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}