Email: jalastru@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Jesús Alastruey Benedé is a Telecommunications Engineer, specializing in Communications, and holds a PhD from the University of Zaragoza (UZ, 1997 and 2009). Since 1999 he has been a professor in the area of Computer Architecture and Technology in the Department of Computer Science and Systems Engineering at the University of Zaragoza, currently as an associate professor. Professor Alastruey is a member of the Computer Architecture research group of the University of Zaragoza (gaZ), and of the Aragon Institute of Engineering Research (I3A). The gaZ participates in the European Network of Excellence HiPEAC and is recognized as a consolidated research group by the Government of Aragon.
Prof. Alastruey has advised two Ph.D thesis and has been a member of the research team in 8 consecutive projects of the National Plan. Some of his work has been published in high impact journals and in prestigious conferences in the area of Computer Architecture. His interests include processor design, performance oriented cache memory hierarchy, high performance programming for parallel architectures and energy saving techniques for multiprocessor chips.
Professor Alastruey’s official profile can be found at:
https://janovas.unizar.es/sideral/CV/jesus-alastruey-benede
And his web page address is:
http://webdiis.unizar.es/u/chus/
PUBLICATIONS
0000
Artículos de revista
Herruzo, Jose M; González-Navarro, Sonia; Ibánez, Pablo; Vinals, Víctor; Alastruey-Benedé, Jesús; Plata, Oscar
Exact Alignment with FM-Index on the Intel Xeon Phi Knights Landing Processor Artículo de revista
En: 0000.
@article{herruzoexact,
title = {Exact Alignment with FM-Index on the Intel Xeon Phi Knights Landing Processor},
author = {Jose M Herruzo and Sonia González-Navarro and Pablo Ibánez and Víctor Vinals and Jesús Alastruey-Benedé and Oscar Plata},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Labari, Alexandra Ferrerón; Obón, Marta Ortín; Gracia, Darío Suárez; Alastruey, Jesús
iLP-NUCA: Cache de Instrucciones Teselada para Procesadores Empotrados Artículo de revista
En: 0000.
@article{labariilp,
title = {iLP-NUCA: Cache de Instrucciones Teselada para Procesadores Empotrados},
author = {Alexandra Ferrerón Labari and Marta Ortín Obón and Darío Suárez Gracia and Jesús Alastruey},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ferrerón, Alexandra; Suárez, Darío; Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor
Low Complexity Improvements for Chip Multiprocessors Shared Caches at Ultra-low Voltages Artículo de revista
En: 0000.
@article{ferreronlow,
title = {Low Complexity Improvements for Chip Multiprocessors Shared Caches at Ultra-low Voltages},
author = {Alexandra Ferrerón and Darío Suárez and Jesús Alastruey and Teresa Monreal and Víctor Viñals},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Alastruey, Jesús; Blasco, Oscar; Ibáñez, Pablo; Briz, José Luis; Viñals, Víctor
SPEC CPU y Caches en Chip: Evolución e Interacción Artículo de revista
En: 0000.
@article{alastrueyspec,
title = {SPEC CPU y Caches en Chip: Evolución e Interacción},
author = {Jesús Alastruey and Oscar Blasco and Pablo Ibáñez and José Luis Briz and Víctor Viñals},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor; Valero, Mateo
Limits on Early Release of Physical Registers Artículo de revista
En: 0000.
@article{alastrueylimits,
title = {Limits on Early Release of Physical Registers},
author = {Jesús Alastruey and Teresa Monreal and Víctor Viñals and Mateo Valero},
keywords = {},
pubstate = {published},
tppubtype = {article}
}