Senior Lecturer
Email: mvg@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
María Villarroya Gaudó obtained her Ph.D. in 2005 at the Department of Electronics Engineering at the Autonoma University of Barcelona. She is an Associate Professor in Computer Architecture and Technology in the Department of Computer and Systems Engineering at the Universidad de Zaragoza. Her research interests include memory hierarchy and heterogeneous systems. Dr. Vilarroya-Gaudó is member of the Aragon Institute of Engineering Research (I3A), the Spanish Society of Computer Architecture (SARTECO).
PUBLICATIONS
2018
Proceedings Articles
Guzman, Maria Angelica Davila; Tejero, Ruben Gran; Gaudo, Maria Villarroya; Gracia, Dario Suarez
Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems Proceedings Article
In: 2018 International Conference on High Performance Computing & Simulation (HPCS), pp. 554–556, IEEE 2018.
@inproceedings{guzman2018towards,
title = {Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems},
author = {Maria Angelica Davila Guzman and Ruben Gran Tejero and Maria Villarroya Gaudo and Dario Suarez Gracia},
year = {2018},
date = {2018-01-01},
booktitle = {2018 International Conference on High Performance Computing & Simulation (HPCS)},
pages = {554--556},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Davila-Guzmán, Maria Angélica; Nozal, Raúl; Rubén, Villarroya-Gaudó María Gran Tejero; Gracia, Darío Suáres; Bosque, Jose Luis
First Steps Towards CPU, GPU, and FPGA Parallel Execution with EngineCL Proceedings Article
In: International Conference Computational and Mathematical Methods in Science and Engineering (CMMSE 2018), pp. 12, 2018.
@inproceedings{davila2018first,
title = {First Steps Towards CPU, GPU, and FPGA Parallel Execution with EngineCL},
author = {Maria Angélica Davila-Guzmán and Raúl Nozal and Villarroya-Gaudó María Gran Tejero Rubén and Darío Suáres Gracia and Jose Luis Bosque},
year = {2018},
date = {2018-01-01},
booktitle = {International Conference Computational and Mathematical Methods in Science and Engineering (CMMSE 2018)},
pages = {12},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2016
Journal Articles
Ortín-Obón, Marta; Suárez-Gracia, Darío; Villarroya-Gaudó, María; Izu, Cruz; Viñals, Víctor
Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs Journal Article
In: Journal of Parallel and Distributed Computing, vol. 95, pp. 57–68, 2016.
@article{ortin2016reactiveb,
title = {Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs},
author = {Marta Ortín-Obón and Darío Suárez-Gracia and María Villarroya-Gaudó and Cruz Izu and Víctor Viñals},
year = {2016},
date = {2016-01-01},
journal = {Journal of Parallel and Distributed Computing},
volume = {95},
pages = {57--68},
publisher = {Academic Press},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ortín-Obón, Marta; Suárez-Gracia, Darío; Villarroya-Gaudó, María; Izu, Cruz; Viñals, Víctor
Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs Journal Article
In: Journal of Parallel and Distributed Computing, vol. 95, pp. 57–68, 2016.
@article{ortin2016reactive,
title = {Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs},
author = {Marta Ortín-Obón and Darío Suárez-Gracia and María Villarroya-Gaudó and Cruz Izu and Víctor Viñals},
year = {2016},
date = {2016-01-01},
journal = {Journal of Parallel and Distributed Computing},
volume = {95},
pages = {57--68},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ortín-Obón, Marta; Suárez-Gracia, Darío; Villarroya-Gaudó, María; Izu, Cruz; Viñals-Yúfera, Víctor
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors Journal Article
In: Microprocessors and Microsystems, vol. 42, pp. 24–36, 2016.
@article{ortin2016analysis,
title = {Analysis of network-on-chip topologies for cost-efficient chip multiprocessors},
author = {Marta Ortín-Obón and Darío Suárez-Gracia and María Villarroya-Gaudó and Cruz Izu and Víctor Viñals-Yúfera},
year = {2016},
date = {2016-01-01},
journal = {Microprocessors and Microsystems},
volume = {42},
pages = {24--36},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}