Senior Lecturer
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)
Email: teresa@ac.upc.edu
Address: Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain
ABOUT ME
Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).
PUBLICATIONS
2019
Journal Articles
Ferrerón-Labari, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Ibáñez-Marín, Pablo; Yúfera, Víctor Viñals
A fault-tolerant last level cache for CMPs operating at ultra-low voltage Journal Article
In: J. Parallel Distributed Comput., vol. 125, pp. 31–44, 2019.
@article{DBLP:journals/jpdc/Ferreron-Labari19,
title = {A fault-tolerant last level cache for CMPs operating at ultra-low
voltage},
author = {Alexandra Ferrerón-Labari and Jesús Alastruey-Benedé and Darío Suárez Gracia and Teresa Monreal Arnal and Pablo Ibáñez-Marín and Víctor Viñals Yúfera},
url = {https://doi.org/10.1016/j.jpdc.2018.10.010},
doi = {10.1016/j.jpdc.2018.10.010},
year = {2019},
date = {2019-01-01},
journal = {J. Parallel Distributed Comput.},
volume = {125},
pages = {31--44},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Blasco, Carlos Escuín; Arnal, Teresa Monreal; Griñó, José M Llaberia; Yúfera, Victor Viñals; Marín, Pablo Ibáñez
STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption Proceedings Article
In: ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts, pp. 231–234, European Network of Excellence on High Performance and Embedded Architecture~… 2019.
@inproceedings{escuin2019stt,
title = {STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption},
author = {Carlos Escuín Blasco and Teresa Monreal Arnal and José M Llaberia Griñó and Victor Viñals Yúfera and Pablo Ibáñez Marín},
year = {2019},
date = {2019-01-01},
booktitle = {ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts},
pages = {231--234},
organization = {European Network of Excellence on High Performance and Embedded Architecture~…},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2017
Journal Articles
Rodríguez-Rodríguez, Roberto; Díaz, Javier; Castro, Fernando; Ibáñez, Pablo; Chaver, Daniel; Viñals, Víctor; Saez, Juan Carlos; Prieto-Matías, Manuel; Piñuel, Luis; Monreal, T; others,
Reuse detector: Improving the management of stt-ram sllcs Journal Article
In: The Computer Journal, vol. 61, no. 6, pp. 856–880, 2017.
@article{rodriguez2017reuse,
title = {Reuse detector: Improving the management of stt-ram sllcs},
author = {Roberto Rodríguez-Rodríguez and Javier Díaz and Fernando Castro and Pablo Ibáñez and Daniel Chaver and Víctor Viñals and Juan Carlos Saez and Manuel Prieto-Matías and Luis Piñuel and T Monreal and others},
year = {2017},
date = {2017-01-01},
journal = {The Computer Journal},
volume = {61},
number = {6},
pages = {856--880},
publisher = {Oxford University Press},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Maag, Javier Díaz; Marín, Pablo Enrique Ibáñez; Arnal, Teresa Monreal; Yúfera, Víctor Viñals; Griñó, José M Llaberia
ReD: A policy based on reuse detection for demanding block selection in last-level Caches Proceedings Article
In: The Second Cache Replacement Championship: workshop schedule, pp. 1–4, 2017.
@inproceedings{diaz2017red,
title = {ReD: A policy based on reuse detection for demanding block selection in last-level Caches},
author = {Javier Díaz Maag and Pablo Enrique Ibáñez Marín and Teresa Monreal Arnal and Víctor Viñals Yúfera and José M Llaberia Griñó},
year = {2017},
date = {2017-01-01},
booktitle = {The Second Cache Replacement Championship: workshop schedule},
pages = {1--4},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2016
Proceedings Articles
Ferrerón, Alexandra; Alastruey, Jesús; Gracía, Dario Suárez; Arnal, Teresa Monreal; Marín, Pablo Enrique Ibáñez; Yúfera, Víctor Viñals
Gestión de contenidos en caches operando a bajo voltaje Proceedings Article
In: XXVI Jornadas de Paralelismo (JP2016): Salamanca, 14-16 septiembre: actas, pp. 497–506, 2016.
@inproceedings{ferreron2016gestion,
title = {Gestión de contenidos en caches operando a bajo voltaje},
author = {Alexandra Ferrerón and Jesús Alastruey and Dario Suárez Gracía and Teresa Monreal Arnal and Pablo Enrique Ibáñez Marín and Víctor Viñals Yúfera},
year = {2016},
date = {2016-01-01},
booktitle = {XXVI Jornadas de Paralelismo (JP2016): Salamanca, 14-16 septiembre: actas},
pages = {497--506},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}