Víctor Soria Pardos

@inproceedings{siracusa2023tensor,

title = {A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors},

author = {M. Siracusa and V. Soria-Pardos and F. Sgherzi and J. Randall and D. J. Joseph and M. Moretó Planas and A. Armejach},

url = {https://dl.acm.org/doi/abs/10.1145/3613424.3614284},

doi = {10.1145/3613424.361428},

year  = {2023},

date = {2023-01-01},

urldate = {2023-01-01},

booktitle = {Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture},

publisher = {ACM},

abstract = {This paper proposes the Tensor Marshaling Unit (TMU), a near-core programmable dataflow engine for multicore architectures that accelerates tensor traversals and merging, the most critical operations of sparse tensor workloads running on today’s computing infrastructures. The TMU leverages a novel multi-lane design that enables parallel tensor loading and merging, which naturally produces vector operands that are marshaled into the core for efficient SIMD computation. The TMU supports all the necessary primitives to be tensor-format and tensor-algebra complete. We evaluate the TMU on a simulated multicore system using a broad set of tensor algebra workloads, achieving 3.6 ×, 2.8 ×, and 4.9 × speedups over memory-intensive, compute-intensive, and merge-intensive vectorized software implementations, respectively.},

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pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{doblas2023sargantana,

title = {Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology},

author = {Max Doblas and Gerard Candón and Xavier Carril and Marc Domínguez and Enric Erra and Alberto González and César Hernández and Víctor Jiménez and Vatistas Kostalampros and Rubén Langarita and Neiel Leyva and Guillem López-Paradís and Jonnatan Mendoza and Josep Oltra and Julián Pavón and Cristóbal Ramírez and Narcís Rodas and Enrico Reggiani and Mario Rodríguez and Carlos Rojas and Abraham Ruiz and Hugo Safadi and Víctor Soria and Alejandro Suanes and Iván Vargas and Fernando Arreza and Roger Figueras and Pau Fontova-Musté and Joan Marimon and Ricardo Martínez and Sergio Moreno and Jordi Sacristán and Oscar Alonso and Xavier Aragonés and Adrián Cristal and Ángel Diéguez and Manuel López and Diego Mateo and Francesc Moll and Miquel Moretó and Oscar Palomar and Marco A Ramírez and Francesc Serra-Graells and Nehir Sonmez and Lluís Terés and Osman Unsal and Mateo Valero and Luis Villa},

doi = {10.1109/DCIS58620.2023.10335976},

year  = {2023},

date = {2023-01-01},

urldate = {2023-01-01},

booktitle = {2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)},

pages = {1–6},

organization = {IEEE},

abstract = {This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM (CSIC). The SoC includes the processor as well as, among other components, a Phase Locked Loop (PLL) operating up to 2 GHz, interfaces to HyperRAM and a Serdes up to 8 Gbps. The processor has demonstrated experimental correct operation at 800 MHz.},

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pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{soria2022sargantana,

title = {Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI},

author = {Víctor Soria-Pardos and Max Doblas and Guillem López–Paradís and Gerard Candón and Narcís Rodas and Xavier Carril and Pau Fontova–Musté and Neiel Leyva and Santiago Marco-Sola and Miquel Moretó},

url = {https://upcommons.upc.edu/server/api/core/bitstreams/df925f8a-5a18-43ab-92c6-a448afa370dc/content},

doi = {10.1109/DSD57027.2022.00042},

year  = {2022},

date = {2022-01-01},

urldate = {2022-01-01},

booktitle = {2022 25th Euromicro Conference on Digital System Design (DSD)},

pages = {254–261},

organization = {IEEE},

abstract = {The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sargantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.},

keywords = {},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{cabo2022dvino,

title = {DVINO: A RISC-V vector processor implemented in 65nm technology},

author = {Guillem Cabo and Gerard Candón and Xavier Carril and Max Doblas and Marc Domínguez and Alberto González and César Hernández and Víctor Jiménez and Vatistas Kostalampros and Rubén Langarita and Neiél Leyva and Guillem López-Paradís and Jonnatan Mendoza and Francesco Minervini and Julián Pavón and Cristóbal Ramírez and Narcís Rodas and Enrico Reggiani and Mario Rodríguez and Carlos Rojas and Abraham Ruiz and Víctor Soria and Alejandro Suanes and Iván Vargas and Roger Figueras and Pau Fontova and Joan Marimon and Víctor Montabes and Adrián Cristal and Carles Hernández and Ricardo Martínez and Miquel Moretó and Francesc Moll and Oscar Palomar and Marco A Ramírez and Antonio Rubio and Jordi Sacristán and Francesc Serra-Graells and Nehir Sonmez and Lluís Terés and Osman Unsal and Mateo Valero and Luís Villa},

url = {https://d1wqtxts1xzle7.cloudfront.net/110413773/dvino-postprint-libre.pdf?1705221936=&response-content-disposition=inline%3B+filename%3DDVINO_A_RISC_V_Vector_Processor_Implemen.pdf&Expires=1767533089&Signature=EOKaJCC8Zgn8ADQB2Lje1L04qUstPgRFdzE8E2oIYEsRYsqf8FByi4dCIS4opSN0r08ESncDVuBIFTsabFuJSenKdS2skWnr1rDGTc9jSTuZ6a-ihhfVeqv-6h~wgS2C~woOEQiPUCvUfBEKEU9eCssL74xiVC3AJ77PFW0ag0OIQGicTqLIDOUyx7Ui5WA31E2Ry-PgjukXMHgNYEgERch51YNqQwK45ezkdnrCBj3Gd8yr4e4wNUezQBQu7DEL6GTtFJoOtncLYi3RK4WKxKwYLq0ToK-mz0WBhDB1X7pOq~7PE8XQ6lRvbRnSxPsDjPc82fmuiKkN12i2Hk9Ozw__&Key-Pair-Id=APKAJLOHF5GGSLRBV4ZA},

doi = {10.1109/DCIS55711.2022.9970128},

year  = {2022},

date = {2022-01-01},

urldate = {2022-01-01},

booktitle = {2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)},

pages = {1–6},

organization = {IEEE},

abstract = {This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.},

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pubstate = {published},

tppubtype = {inproceedings}

}