Email: ktm@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
—
PUBLICATIONS
2015
Artículos de revista
Olivito, Javier; Gran, Rubén; Resano, Javier; González, Carlos; Torres, Enrique
Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors Artículo de revista
En: Microprocessors and Microsystems, vol. 39, no 2, pp. 64–73, 2015.
@article{olivito2015performance,
title = {Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors},
author = {Javier Olivito and Rubén Gran and Javier Resano and Carlos González and Enrique Torres},
year = {2015},
date = {2015-01-01},
journal = {Microprocessors and Microsystems},
volume = {39},
number = {2},
pages = {64--73},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2009
Artículos de revista
Torres, Enrique; Ibanez, Pablo; Llaberia, Jose Maria; others,
Store Buffer Design for Multibanked Data Caches Artículo de revista
En: IEEE Transactions on Computers, vol. 58, no 10, pp. 1307–1320, 2009.
@article{torres2009store,
title = {Store Buffer Design for Multibanked Data Caches},
author = {Enrique Torres and Pablo Ibanez and Jose Maria Llaberia and others},
year = {2009},
date = {2009-01-01},
journal = {IEEE Transactions on Computers},
volume = {58},
number = {10},
pages = {1307--1320},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2007
Artículos de revista
Victorio, JA; Moren, EF Torres; Yúfera, Victor Viñals
Vatios: Simulador de Procesador con Estimación de Potencia. XVIII Jornadas de Paralelismo Artículo de revista
En: Zaragoza, 2007.
@article{victorio2007vatios,
title = {Vatios: Simulador de Procesador con Estimación de Potencia. XVIII Jornadas de Paralelismo},
author = {JA Victorio and EF Torres Moren and Victor Viñals Yúfera},
year = {2007},
date = {2007-01-01},
journal = {Zaragoza},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2005
Proceedings Articles
Torres, Enrique F; Ibánez, Pablo; Viñals, Víctor; Llabería, José María
Store buffer design in first-level multibanked data caches Proceedings Article
En: 32nd International Symposium on Computer Architecture (ISCA’05), pp. 469–480, IEEE 2005.
@inproceedings{torres2005store,
title = {Store buffer design in first-level multibanked data caches},
author = {Enrique F Torres and Pablo Ibánez and Víctor Viñals and José María Llabería},
year = {2005},
date = {2005-01-01},
booktitle = {32nd International Symposium on Computer Architecture (ISCA'05)},
pages = {469--480},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2004
Proceedings Articles
Torres, Enrique F; Ibañez, Pablo; Viñals, Víctor; Llabería, José María
Contents management in first-level multibanked data caches Proceedings Article
En: European Conference on Parallel Processing, pp. 516–524, Springer 2004.
@inproceedings{torres2004contents,
title = {Contents management in first-level multibanked data caches},
author = {Enrique F Torres and Pablo Ibañez and Víctor Viñals and José María Llabería},
year = {2004},
date = {2004-01-01},
booktitle = {European Conference on Parallel Processing},
pages = {516--524},
organization = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}