Alejandro Valero

@article{Muñoz2022,

title = {Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators},

author = {Nicolás Landeros Muñoz and Alejandro Valero and Rubén Gran Tejero and Davide Zoni},

url = {https://www.sciencedirect.com/science/article/pii/S1383762122001072},

doi = {https://doi.org/10.1016/j.sysarc.2022.102553},

issn = {1383-7621},

year  = {2022},

date = {2022-07-01},

urldate = {2022-07-01},

journal = {Journal of Systems Architecture},

volume = {128},

pages = {1-13},

abstract = {Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are two of the main reliability threats in current technology nodes. These aging phenomena degrade the transistor’s threshold voltage (Vth) over the lifetime of a digital circuit, resulting in slower transistors that eventually lead to a faulty operation when the critical paths become longer than the processor cycle time. Among all the transistors on a chip, the most vulnerable transistors to such wearout effects are those used to implement SRAM storage, since memory cells are continuously degrading. In particular, NBTI ages PMOS cell transistors when a given logic value is stored for a long period (i.e., a long duty cycle), whereas HCI ages NMOS cell transistors not only when the stored value flips but also when it is accessed. This work focuses on mitigating aging in the on-chip SRAM memories of Convolutional Neural Network (CNN) accelerators storing activations. This paper makes two main contributions. At the software level, we quantify the aging induced by current CNN benchmarks with a characterization study of duty cycle, flip, and access patterns in every activation memory cell. Based on the insights from this study, this work proposes a novel microarchitectural technique, Gated-CNN, that ensures a uniform aging degradation of every memory cell. To do so, Gated-CNN exploits power-gating and address rotation techniques tailored to the memory demands and temporal/spatial localities exhibited by CNN applications, as well as the memory organization and management of CNN accelerators. Experimental results show that, compared to a conventional design, the average Vth degradation savings are at least as much as 49% depending on the type of transistor.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{DBLP:journals/jpdc/ValeroTGGEAMRI21,

title = {A learning experience toward the understanding of abstraction-level 

 interactions in parallel applications},

author = {Alejandro Valero and Ruben Gran Tejero and Darío Suárez Gracia and Emanuel A. Georgescu and Joaquín Ezpeleta and Pedro Álvarez and Adolfo Muñoz and Luis M. Ramos and Pablo Ibáñez},

url = {https://doi.org/10.1016/j.jpdc.2021.05.008},

doi = {10.1016/j.jpdc.2021.05.008},

year  = {2021},

date = {2021-01-01},

journal = {J. Parallel Distributed Comput.},

volume = {156},

pages = {38--52},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Valero2020,

title = {DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files},

author = {Alejandro Valero and Darío Suárez Gracia and Rubén Gran Tejero},

url = {https://ieeexplore.ieee.org/document/9203907},

doi = {https://doi.org/10.1109/ACCESS.2020.3025899},

issn = {2169-3536},

year  = {2020},

date = {2020-09-22},

urldate = {2020-09-22},

journal = {IEEE Access},

volume = {8},

pages = {173276-173288},

abstract = {The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}