Senior Lecturer
Email: dario@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
—
PUBLICATIONS
2019
Artículos de revista
Rodríguez, Andrés; Navarro, Angeles; Asenjo, Rafael; Corbera, Francisco; Gran, Rubén; Suárez, Darío; Nunez-Yanez, Jose
Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform Artículo de revista
En: The Journal of Supercomputing, pp. 1–21, 2019.
@article{rodriguez2019parallel,
title = {Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform},
author = {Andrés Rodríguez and Angeles Navarro and Rafael Asenjo and Francisco Corbera and Rubén Gran and Darío Suárez and Jose Nunez-Yanez},
year = {2019},
date = {2019-01-01},
journal = {The Journal of Supercomputing},
pages = {1--21},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Rodríguez, Andrés; Navarro, Angeles; Asenjo, Rafael; Corbera, Francisco; Gran, Rubén; Suárez, Darío; Nunez-Yanez, Jose
Exploring Heterogeneous Scheduling for Edge Computing with CPU and FPGA MPSoCs Artículo de revista
En: Journal of Systems Architecture, 2019.
@article{rodriguez2019exploring,
title = {Exploring Heterogeneous Scheduling for Edge Computing with CPU and FPGA MPSoCs},
author = {Andrés Rodríguez and Angeles Navarro and Rafael Asenjo and Francisco Corbera and Rubén Gran and Darío Suárez and Jose Nunez-Yanez},
year = {2019},
date = {2019-01-01},
journal = {Journal of Systems Architecture},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Guzman, Maria Angelica Davila; Nozal, Raúl; Tejero, Rubén Gran; Villarroya-Gaudó, María; Gracia, Darío Suárez; Bosque, Jose Luis
Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL Artículo de revista
En: The Journal of Supercomputing, vol. 75, no 3, pp. 1732–1746, 2019.
@article{guzman2019cooperative,
title = {Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL},
author = {Maria Angelica Davila Guzman and Raúl Nozal and Rubén Gran Tejero and María Villarroya-Gaudó and Darío Suárez Gracia and Jose Luis Bosque},
year = {2019},
date = {2019-01-01},
journal = {The Journal of Supercomputing},
volume = {75},
number = {3},
pages = {1732--1746},
publisher = {Springer US},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ferrerón, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Marín, Pablo Ibáñez; Yúfera, Víctor Viñals
A fault-tolerant last level cache for CMPs operating at ultra-low voltage Artículo de revista
En: Journal of Parallel and Distributed Computing, vol. 125, pp. 31–44, 2019.
@article{ferreron2019fault,
title = {A fault-tolerant last level cache for CMPs operating at ultra-low voltage},
author = {Alexandra Ferrerón and Jesús Alastruey-Benedé and Darío Suárez Gracia and Teresa Monreal Arnal and Pablo Ibáñez Marín and Víctor Viñals Yúfera},
year = {2019},
date = {2019-01-01},
journal = {Journal of Parallel and Distributed Computing},
volume = {125},
pages = {31--44},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ferrerón-Labari, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Ibáñez-Marín, Pablo; Yúfera, Víctor Viñals
A fault-tolerant last level cache for CMPs operating at ultra-low voltage Artículo de revista
En: J. Parallel Distributed Comput., vol. 125, pp. 31–44, 2019.
@article{DBLP:journals/jpdc/Ferreron-Labari19,
title = {A fault-tolerant last level cache for CMPs operating at ultra-low
voltage},
author = {Alexandra Ferrerón-Labari and Jesús Alastruey-Benedé and Darío Suárez Gracia and Teresa Monreal Arnal and Pablo Ibáñez-Marín and Víctor Viñals Yúfera},
url = {https://doi.org/10.1016/j.jpdc.2018.10.010},
doi = {10.1016/j.jpdc.2018.10.010},
year = {2019},
date = {2019-01-01},
journal = {J. Parallel Distributed Comput.},
volume = {125},
pages = {31--44},
keywords = {},
pubstate = {published},
tppubtype = {article}
}