Javier Resano, Associate Professor

I received the Bachelor Degree in Physics in 1997, a Master Degree in Computer Science in 1999, and the PhD degree in 2005 at the Universidad Complutense of Madrid, Spain. I worked eight years as Assistant and Associate Professor at this University, and collaborated with the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. Currently I am Associate Professor at the Computer Eng. Department of the Universidad de Zaragoza (Spain), and a member of the Gaz research group (Computer Architecture group from Universidad of Zaragoza), the Aragón Institute for Engineering Research (I3A) and the High Performance Embedded Architecture and Compilation European Network (HIPEAC). My research has been focused in hardware/software co-design, task scheduling techniques for multi-processor systems, Digital Logic design using FPGAs, and Dynamically Reconfigurable Hardware.

Teaching Activities

I have coordinated of the Bachelor’s Degree in Informatics Engineering from Universidad de Zaragoza during five years. I teach several subjects in this degree related with computer architecture, embedded systems and FPGA design.

In addition I am very active advising final dissertations and PhD thesis. Three of them have received international awards, and eight of them have received especial mentions as the best (or one of the best) dissertation of the year in different degrees, masters and PhD programs. These dissertations typically focus on FPGA design and hardware/software codesign.

Investigación

My research focuses on computer architecture, design of hardware accelerators, remote sensing and application optimization for embedded systems and edge computing. I have published about 50 articles in some of the most important journals and conferences in Computer Architecture, Embedded Systems and Remote Sensing areas collaborating with researches from Universidad Complutense de Madrid, Inter-University Microelectronic Centre of Leuven, Universidad of Extremadura, Puertos del Estado, University of Leicester, Universidad de las Palmas, Hospital Universitario Miguel Servet, and Université de Pau. I am always looking forward for new collaborations.

Currently, I am working on how to improve the efficiency of machine learning techniques reducing its computational cost and energy consumption. In this field, I have designed several hardware accelerators, and shared the designs in public repositories. I also try to develop transparent and reliable models, seeking that the models provide uncertainty metrics and their results are understandable. Finally, I has applied these techniques to real-life problems, like remote-sensing image classification, forecast systems for wave height estimations, or analysis of medical samples with machine learning techniques.

Open collaborations

• Universidad Complutense de Madrid. Collaborating with the GHADIR research group (Group of Dynamically Reconfigurable Hardware)
• Department of Technology of Computers and Communications, University of Extremadura. In this case we are collaborating with Professor Antonio Plaza.
• Universidad de Zaragoza. Collaborating with the Marte (Rapid Methods of Analysis with Spectroscopic Techniques) research group leaded by Professor Martín Resano.

Awards

I am very proud of my experience as a hardware designer. In order to test my abilities, and motivate my students, I participated five times in the FPGA design competition organized by the International Conference on Field-Programmable Technology (FPT). These are the results:

• First prize in the FPGA design competition organized by the 2009 International Conference on Field-Programmable Technology (FPT). Sydney, Australia
• First prize in the FPGA design competition organized by the 2010 International Conference on Field-Programmable Technology (FPT). Beijing, China
• Second prize in the FPGA design competition organized by the 2012 International Conference on Field-Programmable Technology (FPT). Seoul, Korea
• Forth prize in the FPGA design competition organized by the 2013 International Conference on Field-Programmable Technology (FPT). Kioto, Japan
• First prize in the FPGA design competition organized by the 2014 International Conference on Field-Programmable Technology (FPT). Shanghai, China

Other awards:

• IEEE Real World Engineering Projects Award: awarded for a project that illustrated how FPGAs can be used to solve real-world problems
• 800×600 Best Paper Award of an Engineer under 35 years old in the conference SPIE High-Performance Computing in Remote Sensing.