Email: victor@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
—
PUBLICATIONS
2023
Artículos de revista
Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Viñals-Yúfera, Víctor
BALANCER: bandwidth allocation and cache partitioning for multicore processors Artículo de revista
En: The Journal of Supercomputing, pp. 1–25, 2023.
@article{navarro2023balancer,
title = {BALANCER: bandwidth allocation and cache partitioning for multicore processors},
author = {Agustín Navarro-Torres and Jesús Alastruey-Benedé and Pablo Ibáñez and Víctor Viñals-Yúfera},
url = {https://doi.org/10.1007/s11227-023-05070-0},
doi = {10.1007/s11227-023-05070-0},
year = {2023},
date = {2023-01-01},
urldate = {2023-01-01},
journal = {The Journal of Supercomputing},
pages = {1--25},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2022
Proceedings Articles
Gracia, Darío Suárez; Valero, Alejandro; Tejero, Rubén Gran; Villarroya-Gaudó, María; Viñals, Víctor
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter Proceedings Article
En: Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022), pp. 1-6, 2022, ISBN: 978-1-6654-5950-1.
@inproceedings{Gracia2022,
title = {peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter},
author = {Darío Suárez Gracia and Alejandro Valero and Rubén Gran Tejero and María Villarroya-Gaudó and Víctor Viñals},
url = {https://ieeexplore.ieee.org/document/9970050},
doi = {https://doi.org/10.1109/DCIS55711.2022.9970050},
isbn = {978-1-6654-5950-1},
year = {2022},
date = {2022-11-16},
urldate = {2022-11-16},
booktitle = {Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022)},
pages = {1-6},
abstract = {The fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Escuin, Carlos; Khan, Asif Ali; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Castrillón, Jerónimo
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches Proceedings Article
En: DroneSE and RAPIDO ’22: System Engineering for constrained embedded systems, Budapest Hungary, January 17 – 19, 2022, pp. 53–58, ACM, 2022.
@inproceedings{DBLP:conf/hipeac/EscuinKIMVC22,
title = {HyCSim: A rapid design space exploration tool for emerging hybrid
last-level caches},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and Jerónimo Castrillón},
url = {https://doi.org/10.1145/3522784.3522801},
doi = {10.1145/3522784.3522801},
year = {2022},
date = {2022-01-01},
booktitle = {DroneSE and RAPIDO '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {53--58},
publisher = {ACM},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Navarro-Torres, Agustín; Panda, Biswabandan; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Yúfera, Víctor Viñals; Ros, Alberto
Berti: an Accurate Local-Delta Data Prefetcher Proceedings Article
En: 55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022, pp. 975–991, IEEE, 2022.
@inproceedings{DBLP:conf/micro/Navarro-TorresP22,
title = {Berti: an Accurate Local-Delta Data Prefetcher},
author = {Agustín Navarro-Torres and Biswabandan Panda and Jesús Alastruey-Benedé and Pablo Ibáñez and Víctor Viñals Yúfera and Alberto Ros},
url = {https://doi.org/10.1109/MICRO56248.2022.00072},
doi = {10.1109/MICRO56248.2022.00072},
year = {2022},
date = {2022-01-01},
booktitle = {55th IEEE/ACM International Symposium on Microarchitecture, MICRO
2022, Chicago, IL, USA, October 1-5, 2022},
pages = {975--991},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2021
Artículos de revista
Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M
Near-optimal replacement policies for shared caches in multicore processors Artículo de revista
En: The Journal of Supercomputing, pp. 1–30, 2021.
@article{diaz2021near,
title = {Near-optimal replacement policies for shared caches in multicore processors},
author = {Javier Díaz and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and José M Llabería},
year = {2021},
date = {2021-01-01},
journal = {The Journal of Supercomputing},
pages = {1--30},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
}