Senior Lecturer
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)
Email: teresa@ac.upc.edu
Address: Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain
ABOUT ME
Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).
PUBLICATIONS
2022
Proceedings Articles
Escuin, Carlos; Khan, Asif Ali; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Castrillón, Jerónimo
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches Proceedings Article
En: DroneSE and RAPIDO ’22: System Engineering for constrained embedded systems, Budapest Hungary, January 17 – 19, 2022, pp. 53–58, ACM, 2022.
@inproceedings{DBLP:conf/hipeac/EscuinKIMVC22,
title = {HyCSim: A rapid design space exploration tool for emerging hybrid
last-level caches},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and Jerónimo Castrillón},
url = {https://doi.org/10.1145/3522784.3522801},
doi = {10.1145/3522784.3522801},
year = {2022},
date = {2022-01-01},
booktitle = {DroneSE and RAPIDO '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {53--58},
publisher = {ACM},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2021
Artículos de revista
Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M
Near-optimal replacement policies for shared caches in multicore processors Artículo de revista
En: The Journal of Supercomputing, pp. 1–30, 2021.
@article{diaz2021near,
title = {Near-optimal replacement policies for shared caches in multicore processors},
author = {Javier Díaz and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and José M Llabería},
year = {2021},
date = {2021-01-01},
journal = {The Journal of Supercomputing},
pages = {1--30},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M.
Near-optimal replacement policies for shared caches in multicore processors Artículo de revista
En: J. Supercomput., vol. 77, no 10, pp. 11756–11785, 2021.
@article{DBLP:journals/tjs/DiazIMVL21,
title = {Near-optimal replacement policies for shared caches in multicore processors},
author = {Javier Díaz and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and José M. Llabería},
url = {https://doi.org/10.1007/s11227-021-03736-1},
doi = {10.1007/s11227-021-03736-1},
year = {2021},
date = {2021-01-01},
journal = {J. Supercomput.},
volume = {77},
number = {10},
pages = {11756--11785},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2019
Artículos de revista
Díaz, Javier; Monreal, Teresa; Ibáñez, Pablo; Llabería, José M; Viñals, Víctor
ReD: A reuse detector for content selection in exclusive shared last-level caches Artículo de revista
En: Journal of Parallel and Distributed Computing, vol. 125, pp. 106–120, 2019.
@article{diaz2019red,
title = {ReD: A reuse detector for content selection in exclusive shared last-level caches},
author = {Javier Díaz and Teresa Monreal and Pablo Ibáñez and José M Llabería and Víctor Viñals},
year = {2019},
date = {2019-01-01},
journal = {Journal of Parallel and Distributed Computing},
volume = {125},
pages = {106--120},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ferrerón, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Marín, Pablo Ibáñez; Yúfera, Víctor Viñals
A fault-tolerant last level cache for CMPs operating at ultra-low voltage Artículo de revista
En: Journal of Parallel and Distributed Computing, vol. 125, pp. 31–44, 2019.
@article{ferreron2019fault,
title = {A fault-tolerant last level cache for CMPs operating at ultra-low voltage},
author = {Alexandra Ferrerón and Jesús Alastruey-Benedé and Darío Suárez Gracia and Teresa Monreal Arnal and Pablo Ibáñez Marín and Víctor Viñals Yúfera},
year = {2019},
date = {2019-01-01},
journal = {Journal of Parallel and Distributed Computing},
volume = {125},
pages = {31--44},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}