Senior Lecturer
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)
Email: teresa@ac.upc.edu
Address: Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain
ABOUT ME
Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).
PUBLICATIONS
2023
Artículos de revista
Escuin, Carlos; Ibáñez, Pablo; Navarro, Denis; Monreal, Teresa; Llabería, José M; Viñals, Víctor
L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime Artículo de revista
En: Plos one, vol. 18, no 2, pp. e0278346, 2023.
@article{escuin2023l2c2,
title = {L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime},
author = {Carlos Escuin and Pablo Ibáñez and Denis Navarro and Teresa Monreal and José M Llabería and Víctor Viñals},
year = {2023},
date = {2023-01-01},
journal = {Plos one},
volume = {18},
number = {2},
pages = {e0278346},
publisher = {Public Library of Science San Francisco, CA USA},
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Proceedings Articles
Escuin, Carlos; García-Redondo, Fernando; Zahedi, Mahdi; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José María; Myers, James; Ryckaert, Julien; Biswas, Dwaipayan; Catthoor, Francky
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array Proceedings Article
En: 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-5, 2023.
@inproceedings{10382874,
title = {MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array},
author = {Carlos Escuin and Fernando García-Redondo and Mahdi Zahedi and Pablo Ibáñez and Teresa Monreal and Víctor Viñals and José María Llabería and James Myers and Julien Ryckaert and Dwaipayan Biswas and Francky Catthoor},
doi = {10.1109/ICECS58634.2023.10382874},
year = {2023},
date = {2023-01-01},
booktitle = {2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)},
pages = {1-5},
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pubstate = {published},
tppubtype = {inproceedings}
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Escuin, Carlos; Khan, Asif Ali; Ibáñez, Pablo; Monreal, Teresa; Castrillon, Jeronimo; Viñals, Víctor
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs Proceedings Article
En: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 179-192, 2023.
@inproceedings{10070968,
title = {Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibáñez and Teresa Monreal and Jeronimo Castrillon and Víctor Viñals},
doi = {10.1109/HPCA56546.2023.10070968},
year = {2023},
date = {2023-01-01},
booktitle = {2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
pages = {179-192},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
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Escuin, Carlos; Khan, Asif Ali; Ibánez, Pablo; Monreal, Teresa; Navarro, Denis; Llabería, José M; Castrillon, Jeronimo; Viñals, Víctor
Leveraging data compression for performance-efficient and long-lasting nvm-based last-level caches Proceedings Article
En: 14th Annual Non-Volatile Memory Workshop. University of Califronia San Diego, 2023.
@inproceedings{escuin2023leveraging,
title = {Leveraging data compression for performance-efficient and long-lasting nvm-based last-level caches},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibánez and Teresa Monreal and Denis Navarro and José M Llabería and Jeronimo Castrillon and Víctor Viñals},
year = {2023},
date = {2023-01-01},
booktitle = {14th Annual Non-Volatile Memory Workshop. University of Califronia San Diego},
keywords = {},
pubstate = {published},
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2022
Book Sections
Escuin, Carlos; Khan, Asif Ali; Ibañez, Pablo; Monreal, Teresa; Viñals, Victor; Castrillon, Jeronimo
Hycsim: A rapid design space exploration tool for emerging hybrid last-level caches Book Section
En: System Engineering for constrained embedded systems, pp. 53–58, 2022.
@incollection{escuin2022hycsim,
title = {Hycsim: A rapid design space exploration tool for emerging hybrid last-level caches},
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibañez and Teresa Monreal and Victor Viñals and Jeronimo Castrillon},
year = {2022},
date = {2022-01-01},
booktitle = {System Engineering for constrained embedded systems},
pages = {53–58},
keywords = {},
pubstate = {published},
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