Senior Lecturer
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)

Email: teresa@ac.upc.edu

Address: Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain

ABOUT ME

Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).

PUBLICATIONS
45 entries « 1 of 9 »

2022

Proceedings Articles

Escuin, Carlos; Khan, Asif Ali; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Castrillón, Jerónimo

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches Proceedings Article

In: DroneSE and RAPIDO ’22: System Engineering for constrained embedded systems, Budapest Hungary, January 17 – 19, 2022, pp. 53–58, ACM, 2022.

Links | BibTeX

2021

Journal Articles

Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M

Near-optimal replacement policies for shared caches in multicore processors Journal Article

In: The Journal of Supercomputing, pp. 1–30, 2021.

BibTeX

Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M.

Near-optimal replacement policies for shared caches in multicore processors Journal Article

In: J. Supercomput., vol. 77, no. 10, pp. 11756–11785, 2021.

Links | BibTeX

2019

Journal Articles

Díaz, Javier; Monreal, Teresa; Ibáñez, Pablo; Llabería, José M; Viñals, Víctor

ReD: A reuse detector for content selection in exclusive shared last-level caches Journal Article

In: Journal of Parallel and Distributed Computing, vol. 125, pp. 106–120, 2019.

BibTeX

Ferrerón, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Marín, Pablo Ibáñez; Yúfera, Víctor Viñals

A fault-tolerant last level cache for CMPs operating at ultra-low voltage Journal Article

In: Journal of Parallel and Distributed Computing, vol. 125, pp. 31–44, 2019.

BibTeX

45 entries « 1 of 9 »