DESIGN AND OPTIMIZATION OF PERFORMANCE AND ENERGY EFFICIENCY OF APPLICATIONS
Research lines DESIGN AND OPTIMIZATION OF PERFORMANCE AND ENERGY EFFICIENCY OF APPLICATIONS Efficient implementation and tuning of applications is a challenging task. As computer architects, we can identify bottlenecks that…
TASK SCHEDULING AND LOAD BALANCING
Research lines TASK SCHEDULING AND LOAD BALANCING One of the most important challenges to squeeze all the power out of parallel architectures, and specifically of the heterogeneous system, is task…
MEMORY HIERARCHIES FOR REAL-TIME SYSTEMS
Research lines MEMORY HIERARCHIES FOR REAL-TIME SYSTEMS Real-time systems must comply with specific deadlines. This implies that the worst-case execution time (WCET) must be analyzed and bounded at design time.…
ON-CHIP NETWORKS AND MEMORY HIERARCHY
Research lines ON-CHIP NETWORKS AND MEMORY HIERARCHY Today’s processors are highly parallel. There are two main design trends: one toward the implementation of multiprocessor systems with identical cores forming a…