Research lines

On-chip networks and memory hierarchy

Today’s processors are highly parallel. There are two main design trends: one toward the implementation of multiprocessor systems with identical cores forming a homogeneous system and another that encourages heterogeneous systems, in which the architecture of the cores can be different, can operate at different frequencies, and in addition, can be specialized (vectorial, GPUs and other accelerators).

For both types of architectures…

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Memory hierarchies for real-time systems

Real-time systems must comply with specific deadlines. This implies that the worst-case execution time (WCET) must be analyzed and bounded at design time. This is currently feasible for simple processors with an instruction cache, where hits and misses can be predicted. However, the WCET remains unacceptably overestimated for complex processors or conventional data caches. Hence, current hard real-time systems either use simple processors without caches, or oversized architectures.

Our research group studies…

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Task scheduling and load balancing

One of the most important challenges to squeeze all the power out of parallel architectures, and specifically of the heterogeneous system, is task scheduling and load balancing. Generally speaking, the goal is to distribute the workload among the set of compute resources in a parallel architecture, to maximize their utilization…

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Design and optimization of performance and energy efficiency of applications

Efficient implementation and tuning of applications is a challenging task. As computer architects, we can identify bottlenecks that limit performance, and squeeze the compiler options to the limit. As digital-logic designers, we can also develop specific hardware accelerators to achieve significant improvements in energy efficiency and performance. In our previous work…

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