Memory hierarchies for real-time systems

Real-time systems must comply with specific deadlines. This implies that the worst-case execution time (WCET) must be analyzed and bounded at design time. This is currently feasible for simple processors with an instruction cache, where hits and misses can be predicted. However, the WCET remains unacceptably overestimated for complex processors or conventional data caches. Hence, current hard real-time systems either use simple processors without caches, or oversized architectures.

Our research group studies both WCET analysis methods and predictable memory hierarchies whose worst-case behavior can be accurately analyzed.

Ir arriba