On-chip networks and memory hierarchy

Today’s processors are highly parallel. There are two main design trends: one toward the implementation of multiprocessor systems with identical cores forming a homogeneous system and another that encourages heterogeneous systems, in which the architecture of the cores can be different, can operate at different frequencies, and in addition, can be specialized (vectorial, GPUs and other accelerators).

For both types of architectures, which are dominant in today’s market, the memory hierarchy is one of the most critical components. The memory hierarchy within the chip is responsible for providing data to the cores with the appropriate latency and bandwidth. Its structure is complex: several private/shared levels, different content management policies, coherence protocols, etc. As in the cores, there is a trend towards heterogeneity in storage looking for different objectives such as high bandwidth, high capacity, low consumption or low latency. This heterogeneity is manifested both in the organization and in the technology used in its construction.

We are currently working in the performance, efficiency and reliability of the memory hierarchy for:

  • Multicores
  • Accelerators
  • Real-time systems
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