343 entries « 1 of 18 »


Journal Articles

Alcolea, Adrián; Resano, Javier

FPGA Accelerator for Gradient Boosting Decision Trees Journal Article

In: Electronics, vol. 10, no. 3, pp. 314, 2021.


Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M

Near-optimal replacement policies for shared caches in multicore processors Journal Article

In: The Journal of Supercomputing, pp. 1–30, 2021.


Lamela, Adrián; Ossorio, Óscar G; Vinuesa, Guillermo; Sahelices, Benjamín

Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures Journal Article

In: PLOS ONE, vol. 16, no. 9, pp. 1-23, 2021.

Links | BibTeX

Segarra, Juan; Tejero, Ruben Gran; Viñals, Víctor

A generic framework to integrate data caches in the WCET analysis of real-time systems Journal Article

In: J. Syst. Archit., vol. 120, pp. 102304, 2021.

Links | BibTeX


Journal Articles

Moreno, Adrián Alcolea; Olivito, Javier; Resano, Javier; Mecha, Hortensia

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems Journal Article

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 1993–2003, 2020.


Alcolea, Adrián; Paoletti, Mercedes E; Haut, Juan M; Resano, Javier; Plaza, Antonio

Inference in supervised spectral classifiers for on-board hyperspectral imaging: An overview Journal Article

In: Remote Sensing, vol. 12, no. 3, pp. 534, 2020.


Haut, Juan M; Alcolea, Adrian; Paoletti, Mercedes E; Plaza, Javier; Resano, Javier; Plaza, Antonio

GPU-Friendly Neural Networks for Remote Sensing Scene Classification Journal Article

In: IEEE Geoscience and Remote Sensing Letters, 2020.


Pedro-Zapater, Alba; Rodríguez, Clemente; Segarra, Juan; Tejero, Rubén Gran; Viñals-Yúfera, Víctor

Ideal and Predictable Hit Ratio for Matrix Transposition in Data Caches Journal Article

In: Mathematics, vol. 8, no. 2, pp. 184, 2020.


Segarra, Juan; Cortadella, Jordi; Tejero, Rubén Gran; Viñals, Victor

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems with Data Caches Journal Article

In: IEEE Access, 2020.


Pedro-Zapater, Alba; Segarra, Juan; Tejero, Rubén Gran; Viñals, Víctor; Rodríguez, Clemente

Reducing the WCET and analysis time of systems with simple lockable instruction caches Journal Article

In: Plos one, vol. 15, no. 3, pp. e0229980, 2020.



Journal Articles

Nunez-Yanez, Jose; Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Suarez, Dario; Gran, Ruben

Simultaneous multiprocessing in a software-defined heterogeneous FPGA Journal Article

In: The Journal of Supercomputing, vol. 75, no. 8, pp. 4078–4095, 2019.


Desirena-López, G; Ramírez-Treviño, A; Briz, JL; Vázquez, CR; Gómez-Gutiérrez, D

Thermal-aware real-time scheduling using timed continuous petri nets Journal Article

In: ACM Transactions on Embedded Computing Systems (TECS), vol. 18, no. 4, pp. 1–24, 2019.


López, Gaddiel Desirena; Anguiano, Lorena Rubio; Treviño, Antonio Ramírez; Briz, José Luis

A Flexible Framework for Real-Time Thermal-Aware Schedulers using Timed Continuous Petri Nets Journal Article

In: Computación y Sistemas, vol. 23, no. 2, pp. 417–434, 2019.


Candel, Francisco; Valero, Alejandro; Petit, Salvador; Sahuquillo, Julio

Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance Journal Article

In: IEEE Transactions on Computers, vol. 68, no. 10, pp. 1442–1454, 2019.


Rubio-Anguiano, L; Desirena-López, G; Ramírez-Treviño, A; Briz, JL

Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN Journal Article

In: Discrete Event Dynamic Systems, vol. 29, no. 3, pp. 237–264, 2019.


Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez-Marín, Pablo; Viñals-Yúfera, Víctor

Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP Journal Article

In: PloS one, vol. 14, no. 8, pp. e0220135, 2019.


Guzman, Maria Angelica Davila; Nozal, Raúl; Tejero, Rubén Gran; Villarroya-Gaudó, María; Gracia, Darío Suárez; Bosque, Jose Luis

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL Journal Article

In: The Journal of Supercomputing, vol. 75, no. 3, pp. 1732–1746, 2019.


Ferrerón, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Marín, Pablo Ibáñez; Yúfera, Víctor Viñals

A fault-tolerant last level cache for CMPs operating at ultra-low voltage Journal Article

In: Journal of Parallel and Distributed Computing, vol. 125, pp. 31–44, 2019.


Ruiz, José Manuel Herruzo; Gonzalez-Navarro, Sonia; Ibánez, Pablo; Viñals, Victor; Alastruey-Benedé, Jesús; Plata-Gonzalez, Oscar Guillermo; others,

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding Journal Article

In: 2019.


Díaz, Javier; Monreal, Teresa; Ibáñez, Pablo; Llabería, José M; Viñals, Víctor

ReD: A reuse detector for content selection in exclusive shared last-level caches Journal Article

In: Journal of Parallel and Distributed Computing, vol. 125, pp. 106–120, 2019.


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