What is GAZ?

The Computer Architecture Group of Zaragoza (GaZ) is a research group of the University of Zaragoza (UZ). Its members belong to the Department of Computer Science and Systems Engineering (DIIS) and the Engineering Research Institute of Aragon (I3A).

Our current projects share as a common objective to take advantage of the increasing amount of resources of current systems in an efficient way, taking into account both the performance and the energy consumption.

We are working on four main challenges for that purpose:

  • To analyze the design possibilities, both of the interconnection network and the memory hierarchy, to identify solutions that allow the construction of massively parallel and efficient chip systems.
  • To improve the management of available resources in real-time environments, where compliance with temporary restrictions must be guaranteed
  • To develop a series of algorithms and tools that simplify the programming of extremely portable OpenCL applications, both in code, and in relation to their performance and energy consumption
  • To design and accelerate the execution of applications exploiting our knowledge of hardware/software interaction, both in high performance environments and in customized solutions where energy efficiency is a priority

We participate in the HIPEAC European Research Network (High-Performance and Embedded Architecture and Compilation). We also belong to SARTECO, the Spanish Society of Computer Architecture committed to the development of this field in our country.

In addition, our group actively collaborates with a series of Spanish institutions and universities (BSC, Univ. Complutense, Extremadura, Malaga) and also with some foreign ones (U. California Santa Cruz, Toronto Univ. In Canada, U. of Illinois in U.S.A., Univ. of Ferrara in Italy, CINVESTAV Guadalajara in Mexico). Some members of the research team maintain affiliations with other universities such as UPC, Univ. of Valladolid, Univ. of the Basque Country and Univ. of Adelaide (Australia).

Research Lines

ON-CHIP NETWORKS AND MEMORY HIERARCHY
MEMORY HIERARCHIES FOR REAL-TIME SYSTEMS
TASK SCHEDULING AND LOAD BALANCING
DESIGN AND OPTIMIZATION OF PERFORMANCE AND ENERGY EFFICIENCY OF APPLICATIONS
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