Alejandro Valero

@article{Valero2025,

title = {Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches},

author = {Alejandro Valero and Vicente Lorente and Salvador Petit and Julio Sahuquillo},

url = {https://www.computer.org/csdl/journal/tc/2025/08/11022726/27fzlt4rw88},

doi = {10.1109/TC.2025.3575909},

issn = {0018-9340},

year  = {2025},

date = {2025-08-01},

urldate = {2025-08-01},

journal = {IEEE Transactions on Computers},

volume = {74},

number = {8},

pages = {2812-2826},

abstract = {Static Random-Access Memory (SRAM) is the fastest memory technology and has been the common design choice for implementing first-level (L1) caches in the processor pipeline, where speed is a key design issue that must be fulfilled. On the contrary, this technology offers much lower density compared to other technologies like Dynamic RAM, limiting L1 cache sizes of modern processors to a few tens of KB. This paper explores the use of slower but denser Domain Wall Memory (DWM) technology for L1 caches. This technology provides slow access times since it arranges multiple bits sequentially in a magnetic racetrack. To access these bits, they need to be shifted in order to place them under a header. A 1-bit shift usually takes one processor cycle, which can significantly hurt the application performance, making this working behavior inappropriate for L1 caches. Based on the locality (temporal and spatial) principles exploited by caches, this work proposes the Dual Fast-Track Cache (Dual FTC) design, a new approach to organizing a set of racetracks to build set-associative caches. Compared to a conventional SRAM cache, Dual FTC enhances storage capacity by 5× while incurring minimal shifting overhead, thereby rendering it a practical and appealing solution for L1 cache implementations. Experimental results show that the devised cache organization is as fast as an SRAM cache for 78% and 86% of the L1 data cache hits and L1 instruction cache hits, respectively (i.e., no shift is required). Consequently, due to the larger L1 cache capacities, significant system performance gains (by 22% on average) are obtained under the same silicon area.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Toca-Díaz2024,

title = {Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators},

author = {Yamilka Toca-Díaz and Rubén Gran Tejero and Alejandro Valero},

url = {https://www.sciencedirect.com/science/article/pii/S1383762124002297},

doi = {https://doi.org/10.1016/j.sysarc.2024.103292},

issn = {1383-7621},

year  = {2024},

date = {2024-12-01},

urldate = {2024-12-01},

journal = {Journal of Systems Architecture},

volume = {157},

pages = {1-13},

abstract = {Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low Vdd voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at Vmin, respectively.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Toca-Díaz2024b,

title = {Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage},

author = {Yamilka Toca-Díaz and Reynier Hernández Palacios and Ruben Gran Tejero and Alejandro Valero},

url = {https://www.sciencedirect.com/science/article/pii/S0141933124000188},

doi = {https://doi.org/10.1016/j.micpro.2024.105023},

issn = {0141-9331},

year  = {2024},

date = {2024-04-01},

urldate = {2024-04-01},

journal = {Microprocessors and Microsystems},

volume = {106},

pages = {1-13},

abstract = {Aggressively reducing the supply voltage (Vdd) below the safe threshold voltage (Vmin) can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes. This work addresses the impact of permanent faults on the accuracy of a Convolutional Neural Network (CNN) inference accelerator using on-chip activation memories supplied at low Vdd below Vmin. Based on a characterization study of fault patterns, this paper proposes two low-cost microarchitectural techniques, namely Flip-and-Patch, which maintain the original accuracy of CNN applications even in the presence of a high number of faults caused by operating at Vdd < Vmin. Unlike existing techniques, Flip-and-Patch remains transparent to the programmer and does not rely on application characteristics, making it easily applicable to real CNN accelerators.

Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}