Email: victor@unizar.es

Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain

ABOUT ME

PUBLICATIONS
156 entries « 1 of 32 »

2023

Journal Articles

Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Viñals-Yúfera, Víctor

BALANCER: bandwidth allocation and cache partitioning for multicore processors Journal Article

In: The Journal of Supercomputing, pp. 1–25, 2023.

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2022

Proceedings Articles

Escuin, Carlos; Khan, Asif Ali; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Castrillón, Jerónimo

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches Proceedings Article

In: DroneSE and RAPIDO ’22: System Engineering for constrained embedded systems, Budapest Hungary, January 17 – 19, 2022, pp. 53–58, ACM, 2022.

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Navarro-Torres, Agustín; Panda, Biswabandan; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Yúfera, Víctor Viñals; Ros, Alberto

Berti: an Accurate Local-Delta Data Prefetcher Proceedings Article

In: 55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022, pp. 975–991, IEEE, 2022.

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2021

Journal Articles

Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M

Near-optimal replacement policies for shared caches in multicore processors Journal Article

In: The Journal of Supercomputing, pp. 1–30, 2021.

BibTeX

Segarra, Juan; Tejero, Ruben Gran; Viñals, Víctor

A generic framework to integrate data caches in the WCET analysis of real-time systems Journal Article

In: J. Syst. Archit., vol. 120, pp. 102304, 2021.

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156 entries « 1 of 32 »