Email: jolivito@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
—
PUBLICATIONS
2020
Journal Articles
Moreno, Adrián Alcolea; Olivito, Javier; Resano, Javier; Mecha, Hortensia
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 1993–2003, 2020.
@article{moreno2020analysis,
title = {Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems},
author = {Adrián Alcolea Moreno and Javier Olivito and Javier Resano and Hortensia Mecha},
year = {2020},
date = {2020-01-01},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume = {28},
number = {9},
pages = {1993--2003},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2018
Journal Articles
Olivito, Javier; Serrano, Felipe; Clemente, Juan Antonio; Mecha, Hortensia; Resano, Javier
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array Journal Article
In: IET Computers & Digital Techniques, vol. 12, no. 4, pp. 150–157, 2018.
@article{olivito2018analysis,
title = {Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array},
author = {Javier Olivito and Felipe Serrano and Juan Antonio Clemente and Hortensia Mecha and Javier Resano},
year = {2018},
date = {2018-01-01},
journal = {IET Computers & Digital Techniques},
volume = {12},
number = {4},
pages = {150--157},
publisher = {IET},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Moreno, Adrián Alcolea; Olivito, Javier; Resano, Javier
An Efficient Hardware Accelerator to Handle Compressed Filters and Avoid Useless Operations in CNNs Journal Article
In: Jornada de Jóvenes Investigadores del I3A, vol. 6, 2018.
@article{moreno2018efficient,
title = {An Efficient Hardware Accelerator to Handle Compressed Filters and Avoid Useless Operations in CNNs},
author = {Adrián Alcolea Moreno and Javier Olivito and Javier Resano},
year = {2018},
date = {2018-01-01},
journal = {Jornada de Jóvenes Investigadores del I3A},
volume = {6},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2016
Journal Articles
Olivito, Javier; Resano, Javier; Briz, José Luis
Accelerating board games through hardware/software codesign Journal Article
In: IEEE Transactions on Computational Intelligence and AI in Games, vol. 9, no. 4, pp. 393–401, 2016.
@article{olivito2016accelerating,
title = {Accelerating board games through hardware/software codesign},
author = {Javier Olivito and Javier Resano and José Luis Briz},
year = {2016},
date = {2016-01-01},
journal = {IEEE Transactions on Computational Intelligence and AI in Games},
volume = {9},
number = {4},
pages = {393--401},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2015
Journal Articles
Olivito, Javier; Gran, Rubén; Resano, Javier; González, Carlos; Torres, Enrique
Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors Journal Article
In: Microprocessors and Microsystems, vol. 39, no. 2, pp. 64–73, 2015.
@article{olivito2015performance,
title = {Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors},
author = {Javier Olivito and Rubén Gran and Javier Resano and Carlos González and Enrique Torres},
year = {2015},
date = {2015-01-01},
journal = {Microprocessors and Microsystems},
volume = {39},
number = {2},
pages = {64--73},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}