Email: alvabre@unizar.es

Address:
Department of Computer Science and Systems Engineering
Universidad de Zaragoza
Calle María de Luna, 1
Ada Byron Building
50018 Zaragoza, Spain

BIOGRAPHY

Alejandro Valero received the BS, MS, and PhD degrees in Computer Engineering from the Universitat Politècnica de València, Spain, in 2009, 2011, and 2013, respectively. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston, MA, USA, and the University of Cambridge, UK. From 2016 to 2021 he was an Assistant Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain. Since 2021 he is an Associate Professor with the same department and institution. Prof. Valero has taught several courses on computer organization, including Introduction to Computer Systems, Architecture and Organization of Computer Systems, Operating Systems, Data Center Design, and Programming and Architecture of Heterogeneous Computing Systems. His PhD research contributions to the design of high-performance and energy-efficient CPU on-chip memory hierarchies were recognized by multiple entities. He received the Intel Doctoral Student Honor Program Award in 2012 and the Gold Medal in the ACM Student Research Competition (SRC) Award held in the 27th International Conference on Supercomputing (ICS 2013). His current research interests mainly focus on emerging memory technologies, resource management, and the design of GPU and ASIC architectures in terms of performance, energy efficiency, and reliability. Prof. Valero has participated in more than 20 national and local funded projects, some of them as Lead Researcher. He has published more than 30 papers in the main venues of his area such as the International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), IEEE Transactions on Computers, and IEEE Transactions on VLSI Systems. He has served as Program Committee Member in a significant number of conferences, journals, workshops, and research competitions like the Design Automation and Test in Europe (DATE) conference, the International Conference on Computer Design (ICCD), the Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS) workshop, and the ACM SRC Grand Finals. He is also a frequent reviewer in top journals of his area like IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Dependable and Secure Computing, and ACM Transactions on Design Automation of Electronic Systems. He received the Best Reviewer Award in the Design Methods and Tools track at the DATE 2024 conference. Prof. Valero is a member of the Association for Computing Machinery (ACM), the Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), and the Aragon Institute of Engineering Research (I3A).

PUBLICATIONS
41 entries « 1 of 9 »

2025

Journal Articles

Valero, Alejandro; Lorente, Vicente; Petit, Salvador; Sahuquillo, Julio

Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches Journal Article

In: IEEE Transactions on Computers, vol. 74, no. 8, pp. 2812-2826, 2025, ISSN: 0018-9340.

Abstract | Links | BibTeX

2024

Journal Articles

Toca-Díaz, Yamilka; Tejero, Rubén Gran; Valero, Alejandro

Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators Journal Article

In: Journal of Systems Architecture, vol. 157, pp. 1-13, 2024, ISSN: 1383-7621.

Abstract | Links | BibTeX

Toca-Díaz, Yamilka; Palacios, Reynier Hernández; Tejero, Ruben Gran; Valero, Alejandro

Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage Journal Article

In: Microprocessors and Microsystems, vol. 106, pp. 1-13, 2024, ISSN: 0141-9331.

Abstract | Links | BibTeX

Proceedings Articles

Toca-Díaz, Yamilka; Tejero, Rubén Gran; Valero, Alejandro

Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage Proceedings Article

In: pp. 92-95, 2024, ISBN: 979-8-3503-8040-8.

Abstract | Links | BibTeX

2023

Proceedings Articles

Toca-Díaz, Yamilka; Muñoz, Nicolás Landeros; Tejero, Ruben Gran; Valero, Alejandro

On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators Proceedings Article

In: pp. 138-145, 2023, ISBN: 979-8-3503-4419-6.

Abstract | Links | BibTeX

41 entries « 1 of 9 »