Email: alvabre@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Alejandro Valero received the PhD degree in Computer Engineering from the Universitat Politècnica de València, Spain, in 2013. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston, MA, USA, and the University of Cambridge, UK. Since 2016, he has been a Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain, where he teaches several courses on computer organization, including Introduction to Computer Systems, Operating Systems, Data Center Design, and Programming and Architecture of Heterogeneous Computing Systems. His PhD research contributions to the design of high-performance and energy-efficient CPU on-chip memory hierarchies were recognized with the Intel Doctoral Student Honor Program Award and the ACM Student Research Competition Award in 2012 and 2013, respectively. His current research interests mainly focus on emerging memory technologies and the design of GPU and ASIC architectures in terms of performance, energy efficiency, and reliability. Dr. Valero has participated in several national and local funded projects, and has published in the main venues of his area, including the International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), the International Conference on Supercomputing (ICS), IEEE Transactions on Computers, and IEEE Transactions on VLSI Systems. He has served as Program Committee Member and Referee in a significant number of conferences, journals, and workshops. Dr. Valero is a member of the Aragon Institute of Engineering Research (I3A) and the HiPEAC European NoE.
PUBLICATIONS
2015
Journal Articles
Valero, Alejandro; Petit, Salvador; Sahuquillo, Julio; Kaeli, David R; Duato, José
A reuse-based refresh policy for energy-aware eDRAM caches Journal Article
In: Microprocessors and Microsystems, vol. 39, no. 1, pp. 37–48, 2015.
@article{valero2015reuse,
title = {A reuse-based refresh policy for energy-aware eDRAM caches},
author = {Alejandro Valero and Salvador Petit and Julio Sahuquillo and David R Kaeli and José Duato},
year = {2015},
date = {2015-01-01},
journal = {Microprocessors and Microsystems},
volume = {39},
number = {1},
pages = {37--48},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
2014
Journal Articles
Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; López, Pedro; Duato, José
Design of hybrid second-level caches Journal Article
In: IEEE Transactions on Computers, vol. 64, no. 7, pp. 1884–1897, 2014.
@article{valero2014design,
title = {Design of hybrid second-level caches},
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Pedro López and José Duato},
year = {2014},
date = {2014-01-01},
journal = {IEEE Transactions on Computers},
volume = {64},
number = {7},
pages = {1884--1897},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Lorente, Vicente; Valero, Alejandro; Petit, Salvador; Foglia, Pierfrancesco; Sahuquillo, Julio
Analyzing the optimal voltage/frequency pair in fault-tolerant caches Proceedings Article
In: 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC, CSS, ICESS), pp. 19–26, IEEE 2014.
@inproceedings{lorente2014analyzing,
title = {Analyzing the optimal voltage/frequency pair in fault-tolerant caches},
author = {Vicente Lorente and Alejandro Valero and Salvador Petit and Pierfrancesco Foglia and Julio Sahuquillo},
year = {2014},
date = {2014-01-01},
booktitle = {2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC, CSS, ICESS)},
pages = {19--26},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2013
Proceedings Articles
Lorente, Vicente; Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Canal, Ramon; López, Pedro; Duato, José
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes Proceedings Article
In: 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 83–88, IEEE 2013.
@inproceedings{lorente2013combining,
title = {Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes},
author = {Vicente Lorente and Alejandro Valero and Julio Sahuquillo and Salvador Petit and Ramon Canal and Pedro López and José Duato},
year = {2013},
date = {2013-01-01},
booktitle = {2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
pages = {83--88},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Duato, José
Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches Proceedings Article
In: Proceedings of the 27th international ACM conference on International conference on supercomputing, pp. 491–492, 2013.
@inproceedings{valero2013exploiting,
title = {Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches},
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and José Duato},
year = {2013},
date = {2013-01-01},
booktitle = {Proceedings of the 27th international ACM conference on International conference on supercomputing},
pages = {491--492},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}