Email: alvabre@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Alejandro Valero received the PhD degree in Computer Engineering from the Universitat Politècnica de València, Spain, in 2013. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston, MA, USA, and the University of Cambridge, UK. Since 2016, he has been a Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain, where he teaches several courses on computer organization, including Introduction to Computer Systems, Operating Systems, Data Center Design, and Programming and Architecture of Heterogeneous Computing Systems. His PhD research contributions to the design of high-performance and energy-efficient CPU on-chip memory hierarchies were recognized with the Intel Doctoral Student Honor Program Award and the ACM Student Research Competition Award in 2012 and 2013, respectively. His current research interests mainly focus on emerging memory technologies and the design of GPU and ASIC architectures in terms of performance, energy efficiency, and reliability. Dr. Valero has participated in several national and local funded projects, and has published in the main venues of his area, including the International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), the International Conference on Supercomputing (ICS), IEEE Transactions on Computers, and IEEE Transactions on VLSI Systems. He has served as Program Committee Member and Referee in a significant number of conferences, journals, and workshops. Dr. Valero is a member of the Aragon Institute of Engineering Research (I3A) and the HiPEAC European NoE.
PUBLICATIONS
2013
Proceedings Articles
Lorente, Vicente; Valero, Alejandro; Canal, Ramon
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity Proceedings Article
In: European Conference on Parallel Processing, pp. 454–464, Springer 2013.
@inproceedings{lorente2013enhancing,
title = {Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity},
author = {Vicente Lorente and Alejandro Valero and Ramon Canal},
year = {2013},
date = {2013-01-01},
booktitle = {European Conference on Parallel Processing},
pages = {454--464},
organization = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
PhD Theses
Bresó, Alejandro Valero
Hybrid caches: design and data management PhD Thesis
Editorial Universitat Politécnica de Valéncia, 2013.
@phdthesis{valero2013hybrid,
title = {Hybrid caches: design and data management},
author = {Alejandro Valero Bresó},
year = {2013},
date = {2013-01-01},
school = {Editorial Universitat Politécnica de Valéncia},
keywords = {},
pubstate = {published},
tppubtype = {phdthesis}
}
2012
Journal Articles
Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; López, Pedro; Duato, José
Combining recency of information with selective random and a victim cache in last-level caches Journal Article
In: ACM Transactions on Architecture and Code Optimization (TACO), vol. 9, no. 3, pp. 1–20, 2012.
@article{valero2012combining,
title = {Combining recency of information with selective random and a victim cache in last-level caches},
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Pedro López and José Duato},
year = {2012},
date = {2012-01-01},
journal = {ACM Transactions on Architecture and Code Optimization (TACO)},
volume = {9},
number = {3},
pages = {1--20},
publisher = {ACM New York, NY, USA},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Bresó, Alejandro Valero
Disseny de caches de dades L1 mitjançant tecnologia SRAM i eDRAM Journal Article
In: 2012.
@article{valero2012disseny,
title = {Disseny de caches de dades L1 mitjançant tecnologia SRAM i eDRAM},
author = {Alejandro Valero Bresó},
year = {2012},
date = {2012-01-01},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; López, Pedro; Duato, José
Analyzing the optimal ratio of SRAM banks in hybrid caches Proceedings Article
In: 2012 IEEE 30th International Conference on Computer Design (ICCD), pp. 297–302, IEEE 2012.
@inproceedings{valero2012analyzing,
title = {Analyzing the optimal ratio of SRAM banks in hybrid caches},
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Pedro López and José Duato},
year = {2012},
date = {2012-01-01},
booktitle = {2012 IEEE 30th International Conference on Computer Design (ICCD)},
pages = {297--302},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}