Email: alvabre@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Alejandro Valero received the PhD degree in Computer Engineering from the Universitat Politècnica de València, Spain, in 2013. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston, MA, USA, and the University of Cambridge, UK. Since 2016, he has been a Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain, where he teaches several courses on computer organization, including Introduction to Computer Systems, Operating Systems, Data Center Design, and Programming and Architecture of Heterogeneous Computing Systems. His PhD research contributions to the design of high-performance and energy-efficient CPU on-chip memory hierarchies were recognized with the Intel Doctoral Student Honor Program Award and the ACM Student Research Competition Award in 2012 and 2013, respectively. His current research interests mainly focus on emerging memory technologies and the design of GPU and ASIC architectures in terms of performance, energy efficiency, and reliability. Dr. Valero has participated in several national and local funded projects, and has published in the main venues of his area, including the International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), the International Conference on Supercomputing (ICS), IEEE Transactions on Computers, and IEEE Transactions on VLSI Systems. He has served as Program Committee Member and Referee in a significant number of conferences, journals, and workshops. Dr. Valero is a member of the Aragon Institute of Engineering Research (I3A) and the HiPEAC European NoE.
PUBLICATIONS
2009
Proceedings Articles
Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal, Ramon; López, Pedro; Duato, José
An hybrid eDRAM/SRAM macrocell to implement first-level data caches Proceedings Article
In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 213–221, ACM 2009.
@inproceedings{valero2009hybrid,
title = {An hybrid eDRAM/SRAM macrocell to implement first-level data caches},
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Vicente Lorente and Ramon Canal and Pedro López and José Duato},
year = {2009},
date = {2009-01-01},
booktitle = {Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture},
pages = {213--221},
organization = {ACM},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
0000
Journal Articles
Valero, Alejandro; Gracia, Darío Suárez; Tejero, Rubén Gran; Ramos, Luis M; Navarro-Torres, Agustín; Munoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Murillo, Ana C; Montijano, Eduardo; others,
Experimentacion Preliminar con un Trazador de Rayos para Relacionar Niveles de Abstraccion Journal Article
In: 0000.
@article{valeroexperimentacion,
title = {Experimentacion Preliminar con un Trazador de Rayos para Relacionar Niveles de Abstraccion},
author = {Alejandro Valero and Darío Suárez Gracia and Rubén Gran Tejero and Luis M Ramos and Agustín Navarro-Torres and Adolfo Munoz and Joaquín Ezpeleta and José Luis Briz and Ana C Murillo and Eduardo Montijano and others},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Lorente, Vicente; Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; López, Pedro; Duato, José
Cache Híbrida de Primer Nivel Tolerante a Fallos Journal Article
In: 0000.
@article{lorentecache,
title = {Cache Híbrida de Primer Nivel Tolerante a Fallos},
author = {Vicente Lorente and Alejandro Valero and Julio Sahuquillo and Salvador Petit and Pedro López and José Duato},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Duato, José
Política de Refresco Selectiva para Memorias Cache eDRAM Journal Article
In: 0000.
@article{valeropolitica,
title = {Política de Refresco Selectiva para Memorias Cache eDRAM},
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and José Duato},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Valero, Alejandro; Lorente, Vicente; Sahuquillo, Júlio; Petit, Salvador; López, Pedro; Duato, José
Memoria dinámica en caches de datos de primer nivel sin necesidad de refresco Journal Article
In: 0000.
@article{valeromemoria,
title = {Memoria dinámica en caches de datos de primer nivel sin necesidad de refresco},
author = {Alejandro Valero and Vicente Lorente and Júlio Sahuquillo and Salvador Petit and Pedro López and José Duato},
keywords = {},
pubstate = {published},
tppubtype = {article}
}