Skip to content
Menu
Home
Research lines
ON-CHIP NETWORKS AND MEMORY HIERARCHY
MEMORY HIERARCHIES FOR REAL-TIME SYSTEMS
TASK SCHEDULING AND LOAD BALANCING
DESIGN AND OPTIMIZATION OF PERFORMANCE AND ENERGY EFFICIENCY OF APPLICATIONS
Projects
Team
Publications
Repositories
FPGA for GBDT
POLYGAZ
MATRIX TRANSPOSITION
BVSFM
SPARSE ACCELERATOR
TERTIMUSS
News
Former Members
María Angélica Dávila Guzmán
12 April 2023
24 January 2023
by
i3a
Alba Pedro Zapater
24 January 2023
by
i3a
