Senior Lecturer

Email: dario@unizar.es

Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain

ABOUT ME

PUBLICATIONS
60 entries « 1 of 12 »

2022

Proceedings Articles

Gracia, Darío Suárez; Valero, Alejandro; Tejero, Rubén Gran; Villarroya-Gaudó, María; Viñals, Víctor

peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter Proceedings Article

In: Proceedings of the 37th Conference on Design of Circuits and Integrated Circuits (DCIS 2022), pp. 1-6, 2022, ISBN: 978-1-6654-5950-1.

Abstract | Links | BibTeX

2021

Journal Articles

Valero, Alejandro; Tejero, Ruben Gran; Gracia, Darío Suárez; Georgescu, Emanuel A.; Ezpeleta, Joaquín; Álvarez, Pedro; Muñoz, Adolfo; Ramos, Luis M.; Ibáñez, Pablo

A learning experience toward the understanding of abstraction-level interactions in parallel applications Journal Article

In: J. Parallel Distributed Comput., vol. 156, pp. 38–52, 2021.

Links | BibTeX

2020

Journal Articles

Valero, Alejandro; Gracia, Darío Suárez; Tejero, Rubén Gran

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files Journal Article

In: IEEE Access, vol. 8, pp. 173276-173288, 2020, ISSN: 2169-3536.

Abstract | Links | BibTeX

2019

Journal Articles

Nunez-Yanez, Jose; Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Suarez, Dario; Gran, Ruben

Simultaneous multiprocessing in a software-defined heterogeneous FPGA Journal Article

In: The Journal of Supercomputing, vol. 75, no. 8, pp. 4078–4095, 2019.

BibTeX

Rodríguez, Andrés; Navarro, Angeles; Asenjo, Rafael; Corbera, Francisco; Gran, Rubén; Suárez, Darío; Nunez-Yanez, Jose

Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform Journal Article

In: The Journal of Supercomputing, pp. 1–21, 2019.

BibTeX

60 entries « 1 of 12 »