University of Zaragoza
Alejandro Valero received the PhD degree in Computer Engineering from the Universitat Politècnica de València, Spain, in 2013. From 2013 to 2015 he was a Visiting Researcher with Northeastern University, Boston, MA, USA, and the University of Cambridge, UK. Since 2016, he has been a Professor with the Department of Computer Science and Systems Engineering, Universidad de Zaragoza, Spain, where he teaches several courses on computer organization, including Introduction to Computer Systems, Operating Systems, Data Center Design, and Programming and Architecture of Heterogeneous Computing Systems. His PhD research contributions to the design of high-performance and energy-efficient CPU on-chip memory hierarchies were recognized with the Intel Doctoral Student Honor Program Award and the ACM Student Research Competition Award in 2012 and 2013, respectively. His current research interests mainly focus on emerging memory technologies and the design of GPU and ASIC architectures in terms of performance, energy efficiency, and reliability. Dr. Valero has participated in several national and local funded projects, and has published in the main venues of his area, including the International Symposium on Microarchitecture (MICRO), the International Conference on Parallel Architectures and Compilation Techniques (PACT), the International Conference on Supercomputing (ICS), IEEE Transactions on Computers, and IEEE Transactions on VLSI Systems. He has served as Program Committee Member and Referee in a significant number of conferences, journals, and workshops. Dr. Valero is a member of the Aragon Institute of Engineering Research (I3A) and the HiPEAC European NoE.
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance Journal Article
In: IEEE Transactions on Computers, 68 (10), pp. 1442–1454, 2019.
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer Inproceedings
In: Proceedings of the Workshop on Computer Architecture Education, pp. 1–8, 2019.
Atomicidad, Consistencia, Paralelismo y Concurrencia en un Trazador de Rayos elaborado a lo largo del Grado en Ingeniería Informatica Journal Article
In: Actas de las XXIX Jornadas de Paralelismo, pp. 201–207, 2018.
An Aging-Aware GPU Register File Design Based on Data Redundancy Journal Article
In: IEEE Transactions on Computers, 68 (1), pp. 4–20, 2018.
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache Inproceedings
In: European Conference on Parallel Processing, pp. 235–248, Springer 2018.