Email: jalastru@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Jesús Alastruey Benedé is a Telecommunications Engineer, specializing in Communications, and holds a PhD from the University of Zaragoza (UZ, 1997 and 2009). Since 1999 he has been a professor in the area of Computer Architecture and Technology in the Department of Computer Science and Systems Engineering at the University of Zaragoza, currently as an associate professor. Professor Alastruey is a member of the Computer Architecture research group of the University of Zaragoza (gaZ), and of the Aragon Institute of Engineering Research (I3A). The gaZ participates in the European Network of Excellence HiPEAC and is recognized as a consolidated research group by the Government of Aragon.
Prof. Alastruey has advised two Ph.D thesis and has been a member of the research team in 8 consecutive projects of the National Plan. Some of his work has been published in high impact journals and in prestigious conferences in the area of Computer Architecture. His interests include processor design, performance oriented cache memory hierarchy, high performance programming for parallel architectures and energy saving techniques for multiprocessor chips.
Professor Alastruey’s official profile can be found at:
https://janovas.unizar.es/sideral/CV/jesus-alastruey-benede
And his web page address is:
http://webdiis.unizar.es/u/chus/
PUBLICATIONS
2009
Journal Articles
Alastruey, Jesús; Monreal, Teresa; Valero, M; Viñals, V
Implementación de un Predictor de último Uso con Decaimiento Journal Article
In: XX Jornadas de Paralelismo, La Coruña (España), pp. 17–18, 2009.
@article{alastruey2009implementacion,
title = {Implementación de un Predictor de último Uso con Decaimiento},
author = {Jesús Alastruey and Teresa Monreal and M Valero and V Viñals},
year = {2009},
date = {2009-01-01},
journal = {XX Jornadas de Paralelismo, La Coruña (España)},
pages = {17--18},
keywords = {},
pubstate = {published},
tppubtype = {article}
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2008
Proceedings Articles
Alastruey, Jesús; Monreal, Teresa; Cazorla, Francisco; Viñals, Víctor; Valero, Mateo
Selection of the register file size and the resource allocation policy on SMT processors Proceedings Article
In: 2008 20th International Symposium on Computer Architecture and High Performance Computing, pp. 63–70, IEEE 2008.
@inproceedings{alastruey2008selection,
title = {Selection of the register file size and the resource allocation policy on SMT processors},
author = {Jesús Alastruey and Teresa Monreal and Francisco Cazorla and Víctor Viñals and Mateo Valero},
year = {2008},
date = {2008-01-01},
booktitle = {2008 20th International Symposium on Computer Architecture and High Performance Computing},
pages = {63--70},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
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2007
Proceedings Articles
Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor; Valero, Mateo
Microarchitectural support for speculative register renaming Proceedings Article
In: 2007 IEEE International Parallel and Distributed Processing Symposium, pp. 1–10, IEEE 2007.
@inproceedings{alastruey2007microarchitecturalb,
title = {Microarchitectural support for speculative register renaming},
author = {Jesús Alastruey and Teresa Monreal and Víctor Viñals and Mateo Valero},
year = {2007},
date = {2007-01-01},
booktitle = {2007 IEEE International Parallel and Distributed Processing Symposium},
pages = {1--10},
organization = {IEEE},
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Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor; Valero, Mateo
Microarchitectural support for speculative register renaming Proceedings Article
In: 2007 IEEE International Parallel and Distributed Processing Symposium, pp. 1–10, IEEE 2007.
@inproceedings{alastruey2007microarchitectural,
title = {Microarchitectural support for speculative register renaming},
author = {Jesús Alastruey and Teresa Monreal and Víctor Viñals and Mateo Valero},
year = {2007},
date = {2007-01-01},
booktitle = {2007 IEEE International Parallel and Distributed Processing Symposium},
pages = {1--10},
organization = {IEEE},
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Alastruey, Jesús; Arnal, Teresa Monreal; Almeida, Francisco Javier Cazorla; Yúfera, Víctor Viñals; Cortés, Mateo Valero
Selección del Tamaño del Banco de Registros y de la Política de Asignación de Recursos en Procesadores SMT Proceedings Article
In: Actas de las XVIII Jornadas de Paralelismo, volumen 1: Zaragoza, 12-14 septiembre 2007, pp. 3–10, Thomson Editores Spain 2007.
@inproceedings{alastruey2007seleccion,
title = {Selección del Tamaño del Banco de Registros y de la Política de Asignación de Recursos en Procesadores SMT},
author = {Jesús Alastruey and Teresa Monreal Arnal and Francisco Javier Cazorla Almeida and Víctor Viñals Yúfera and Mateo Valero Cortés},
year = {2007},
date = {2007-01-01},
booktitle = {Actas de las XVIII Jornadas de Paralelismo, volumen 1: Zaragoza, 12-14 septiembre 2007},
pages = {3--10},
organization = {Thomson Editores Spain},
keywords = {},
pubstate = {published},
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}