Email: jalastru@unizar.es

Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain

ABOUT ME

Jesús Alastruey Benedé is a Telecommunications Engineer, specializing in Communications, and holds a PhD from the University of Zaragoza (UZ, 1997 and 2009). Since 1999 he has been a professor in the area of Computer Architecture and Technology in the Department of Computer Science and Systems Engineering at the University of Zaragoza, currently as an associate professor. Professor Alastruey is a member of the Computer Architecture research group of the University of Zaragoza (gaZ), and of the Aragon Institute of Engineering Research (I3A). The gaZ participates in the European Network of Excellence HiPEAC and is recognized as a consolidated research group by the Government of Aragon.

Prof. Alastruey has advised a Ph.D thesis and has been a member of the research team in 7 consecutive projects of the National Plan. Some of his work has been published in high impact journals and in prestigious conferences in the area of Computer Architecture. His interests include processor design, performance oriented cache memory hierarchy, high performance programming for parallel architectures and energy saving techniques for multiprocessor chips.

Professor Alastruey’s official profile can be found at:
https://janovas.unizar.es/sideral/CV/jesus-alastruey-benede
And his web page address is:
http://webdiis.unizar.es/u/chus/

PUBLICATIONS
39 entries « 6 of 8 »

2007

Proceedings Articles

Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor; Valero, Mateo

Microarchitectural support for speculative register renaming Proceedings Article

In: 2007 IEEE International Parallel and Distributed Processing Symposium, pp. 1–10, IEEE 2007.

BibTeX

Alastruey, Jesús; Arnal, Teresa Monreal; Almeida, Francisco Javier Cazorla; Yúfera, Víctor Viñals; Cortés, Mateo Valero

Selección del Tamaño del Banco de Registros y de la Política de Asignación de Recursos en Procesadores SMT Proceedings Article

In: Actas de las XVIII Jornadas de Paralelismo, volumen 1: Zaragoza, 12-14 septiembre 2007, pp. 3–10, Thomson Editores Spain 2007.

BibTeX

2006

Journal Articles

Alastruey, Jesús; Briz, José Luis; Ibáñez, Pablo; Viñals, Victor

Software demand, hardware supply Journal Article

In: IEEE Micro, vol. 26, no. 4, pp. 72–82, 2006.

BibTeX

Proceedings Articles

Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor; Valero, Mateo

Speculative early register release Proceedings Article

In: Proceedings of the 3rd conference on Computing frontiers, pp. 291–302, ACM 2006.

BibTeX

2004

Proceedings Articles

Cortés, Mateo Valero; Benedé, Jesús Alastruey; Monreal, Teresa; Yufera, Víctor Viñals

Limits on Early Relase of Phisical Registers Proceedings Article

In: Computación de altas prestaciones: actas de las XV Jornadas de Paralelismo, Almería, 15, 16 y 17 de septiembre de 2004, pp. 231–236, Servicio de Publicaciones 2004.

BibTeX

39 entries « 6 of 8 »