Address

Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain

Contact Information

Email: rgran@unizar.es

Rubén Gran Tejero

Senior Lecturer

University of Zaragoza

Biography

Rubén Gran Tejero graduated in Computer Science from the University of Zaragoza, Spain. He received his Ph.D. from the Polytechnic University of Catalonia (UPC), Spain, in 2010. Since 2010, he has been an Associate Professor at the Department of Computer Science and Systems Engineering, University of Zaragoza. His research interests include hard real-time systems, hardware for reducing worst-case execution time and energy consumption, efficient processor microarchitecture, and effective programming for parallel and heterogeneous systems. Dr. Gran Tejero is member of the Aragon Institute of Engineering Research (I3A) and the Spanish Society of Computer Architecture (SARTECO).

Publications

42 entries « 1 of 9 »

2021

Journal Articles

Segarra, Juan; Tejero, Ruben Gran; Viñals, Víctor

A generic framework to integrate data caches in the WCET analysis of real-time systems Journal Article

In: J. Syst. Archit., 120 , pp. 102304, 2021.

Links | BibTeX

2020

Journal Articles

Pedro-Zapater, Alba; Rodríguez, Clemente; Segarra, Juan; Tejero, Rubén Gran; Viñals-Yúfera, Víctor

Ideal and Predictable Hit Ratio for Matrix Transposition in Data Caches Journal Article

In: Mathematics, 8 (2), pp. 184, 2020.

BibTeX

Segarra, Juan; Cortadella, Jordi; Tejero, Rubén Gran; Viñals, Victor

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems with Data Caches Journal Article

In: IEEE Access, 2020.

BibTeX

Pedro-Zapater, Alba; Segarra, Juan; Tejero, Rubén Gran; Viñals, Víctor; Rodríguez, Clemente

Reducing the WCET and analysis time of systems with simple lockable instruction caches Journal Article

In: Plos one, 15 (3), pp. e0229980, 2020.

BibTeX

2019

Journal Articles

Rodríguez, Andrés; Navarro, Angeles; Asenjo, Rafael; Corbera, Francisco; Gran, Rubén; Suárez, Darío; Nunez-Yanez, Jose

Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform Journal Article

In: The Journal of Supercomputing, pp. 1–21, 2019.

BibTeX

42 entries « 1 of 9 »
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