Email: jalastru@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Jesús Alastruey Benedé is a Telecommunications Engineer, specializing in Communications, and holds a PhD from the University of Zaragoza (UZ, 1997 and 2009). Since 1999 he has been a professor in the area of Computer Architecture and Technology in the Department of Computer Science and Systems Engineering at the University of Zaragoza, currently as an associate professor. Professor Alastruey is a member of the Computer Architecture research group of the University of Zaragoza (gaZ), and of the Aragon Institute of Engineering Research (I3A). The gaZ participates in the European Network of Excellence HiPEAC and is recognized as a consolidated research group by the Government of Aragon.
Prof. Alastruey has advised a Ph.D thesis and has been a member of the research team in 7 consecutive projects of the National Plan. Some of his work has been published in high impact journals and in prestigious conferences in the area of Computer Architecture. His interests include processor design, performance oriented cache memory hierarchy, high performance programming for parallel architectures and energy saving techniques for multiprocessor chips.
Professor Alastruey’s official profile can be found at:
https://janovas.unizar.es/sideral/CV/jesus-alastruey-benede
And his web page address is:
http://webdiis.unizar.es/u/chus/
PUBLICATIONS
2002
Proceedings Articles
Ibáñez, Pablo; Benedé, Jesús Alastruey; Cruz, Oscar Blasco; Yufera, Víctor Viñals; Velasco, José Luis Briz
SPEC CPUy caches en chip: evolución e interacción Proceedings Article
In: XIII Jornadas de Paralelismo: Lleida, 9, 10 y 11 de septiembre de 2002: actas, pp. 19–24, Universitat de Lleida 2002.
@inproceedings{ibanez2002spec,
title = {SPEC CPUy caches en chip: evolución e interacción},
author = {Pablo Ibáñez and Jesús Alastruey Benedé and Oscar Blasco Cruz and Víctor Viñals Yufera and José Luis Briz Velasco},
year = {2002},
date = {2002-01-01},
booktitle = {XIII Jornadas de Paralelismo: Lleida, 9, 10 y 11 de septiembre de 2002: actas},
pages = {19--24},
organization = {Universitat de Lleida},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
1791
Journal Articles
Serrano-Gracia, María Astón; Kjelgaard-Mikkelsen, Carl Christian; Alastruey-Benedé, Jesús; Ibáñez-Marín, Pablo; García-Risueño, Pablo; Ortín, M; Ramini, L; Tatenguem, H; Viñals, V; Bertozzi, D; others,
Implementació? n de un nuevo algoritmo para imponer ligaduras en Diná? mica Molecular Journal Article
In: XXV Jornadas de Paralelismo, vol. 1, pp. 3–10, 1791.
@article{serrano1791implementacio,
title = {Implementació? n de un nuevo algoritmo para imponer ligaduras en Diná? mica Molecular},
author = {María Astón Serrano-Gracia and Carl Christian Kjelgaard-Mikkelsen and Jesús Alastruey-Benedé and Pablo Ibáñez-Marín and Pablo García-Risueño and M Ortín and L Ramini and H Tatenguem and V Viñals and D Bertozzi and others},
year = {1791},
date = {1791-01-01},
journal = {XXV Jornadas de Paralelismo},
volume = {1},
pages = {3--10},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
0000
Journal Articles
Herruzo, Jose M; González-Navarro, Sonia; Ibánez, Pablo; Vinals, Víctor; Alastruey-Benedé, Jesús; Plata, Oscar
Exact Alignment with FM-Index on the Intel Xeon Phi Knights Landing Processor Journal Article
In: 0000.
@article{herruzoexact,
title = {Exact Alignment with FM-Index on the Intel Xeon Phi Knights Landing Processor},
author = {Jose M Herruzo and Sonia González-Navarro and Pablo Ibánez and Víctor Vinals and Jesús Alastruey-Benedé and Oscar Plata},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Labari, Alexandra Ferrerón; Obón, Marta Ortín; Gracia, Darío Suárez; Alastruey, Jesús
iLP-NUCA: Cache de Instrucciones Teselada para Procesadores Empotrados Journal Article
In: 0000.
@article{labariilp,
title = {iLP-NUCA: Cache de Instrucciones Teselada para Procesadores Empotrados},
author = {Alexandra Ferrerón Labari and Marta Ortín Obón and Darío Suárez Gracia and Jesús Alastruey},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Ferrerón, Alexandra; Suárez, Darío; Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor
Low Complexity Improvements for Chip Multiprocessors Shared Caches at Ultra-low Voltages Journal Article
In: 0000.
@article{ferreronlow,
title = {Low Complexity Improvements for Chip Multiprocessors Shared Caches at Ultra-low Voltages},
author = {Alexandra Ferrerón and Darío Suárez and Jesús Alastruey and Teresa Monreal and Víctor Viñals},
keywords = {},
pubstate = {published},
tppubtype = {article}
}