Senior Lecturer
Email: briz@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
José Luis Briz is a tenured Associate Professor in the Department of Computer and Systems Engineering at the UZ. His research interests include memory hierarchy and processor microarchitecture, and is currently involved in thermal-aware real-time scheduling on MPSoCs. He does also collaborate in embedded systems projects with the industry. Briz has a combined BS/MS degree in Geology, a MS degree in Computer Science, and a PhD in Computer Engineering, all of them from UZ, having published some contributions to the application of computing to Structural Geology. He is a member of the gaZ group, the I3A Research Institute, and Affiliate of the HiPEAC European Network of Excellence. He is also a member of the ISOC and of the Spanish Society of Computer Architecture (SARTECO)
PUBLICATIONS
2019
Miscellaneous
Desirena, G; Rubio, L; Ramirez, A; Briz, JL
Thermal-aware hrt scheduling simulation framework Miscellaneous
2019.
@misc{desirena2019thermalb,
title = {Thermal-aware hrt scheduling simulation framework},
author = {G Desirena and L Rubio and A Ramirez and JL Briz},
year = {2019},
date = {2019-01-01},
keywords = {},
pubstate = {published},
tppubtype = {misc}
}
Workshops
Valero, Alejandro; Gracia, Darío Suárez; Tejero, Ruben Gran; Ramos, Luis M.; Navarro-Torres, Agustín; Muñoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Murillo, Ana C.; Montijano, Eduardo; Resano, Javier; Villarroya-Gaudó, María; Alastruey-Benedé, Jesús; Torres, Enrique F.; Álvarez, Pedro; Ibáñez, Pablo; Viñals, Víctor
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer Workshop
Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA 2019, Phoenix, AZ, USA, June 22, 2019, ACM, 2019.
@workshop{DBLP:conf/wcae/ValeroGTRNMEBMM19,
title = {Exposing Abstraction-Level Interactions with a Parallel Ray Tracer},
author = {Alejandro Valero and Darío Suárez Gracia and Ruben Gran Tejero and Luis M. Ramos and Agustín Navarro-Torres and Adolfo Muñoz and Joaquín Ezpeleta and José Luis Briz and Ana C. Murillo and Eduardo Montijano and Javier Resano and María Villarroya-Gaudó and Jesús Alastruey-Benedé and Enrique F. Torres and Pedro Álvarez and Pablo Ibáñez and Víctor Viñals},
url = {https://doi.org/10.1145/3338698.3338886},
doi = {10.1145/3338698.3338886},
year = {2019},
date = {2019-01-01},
urldate = {2019-01-01},
booktitle = {Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA
2019, Phoenix, AZ, USA, June 22, 2019},
pages = {5:1--5:8},
publisher = {ACM},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
2018
Journal Articles
Possignolo, Rafael Trapani; Ebrahimi, Elnaz; Ardestani, Ehsan Khish; Sankaranarayanan, Alamelu; Briz, Jose Luis; Renau, Jose
Gpu ntc process variation compensation with voltage stacking Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 9, pp. 1713–1726, 2018.
@article{possignolo2018gpu,
title = {Gpu ntc process variation compensation with voltage stacking},
author = {Rafael Trapani Possignolo and Elnaz Ebrahimi and Ehsan Khish Ardestani and Alamelu Sankaranarayanan and Jose Luis Briz and Jose Renau},
year = {2018},
date = {2018-01-01},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume = {26},
number = {9},
pages = {1713--1726},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Rubio-Anguiano, L; Desirena-López, G; Ramírez-Treviño, A; Briz, JL
Energy-Efficient Thermal-Aware Scheduling for RT Tasks Using TCPN Journal Article
In: IFAC-PapersOnLine, vol. 51, no. 7, pp. 236–242, 2018.
@article{rubio2018energy,
title = {Energy-Efficient Thermal-Aware Scheduling for RT Tasks Using TCPN},
author = {L Rubio-Anguiano and G Desirena-López and A Ramírez-Treviño and JL Briz},
year = {2018},
date = {2018-01-01},
journal = {IFAC-PapersOnLine},
volume = {51},
number = {7},
pages = {236--242},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings
Valero, Alejandro; Gracia, Darío Suárez; Gran, Rubén; Munoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Ramos, Luis M; Murillo, Ana C; Montijano, Eduardo; Resano, Javier; others,
Actas de las Jornadas SARTECO 2018, 2018.
@proceedings{valero2018atomicidad,
title = {Atomicidad, Consistencia, Paralelismo y Concurrencia en un Trazador de Rayos elaborado a lo largo del Grado en Ingeniería Informática},
author = {Alejandro Valero and Darío Suárez Gracia and Rubén Gran and Adolfo Munoz and Joaquín Ezpeleta and José Luis Briz and Luis M Ramos and Ana C Murillo and Eduardo Montijano and Javier Resano and others},
url = {https://zenodo.org/records/1303185},
doi = {https://doi.org/10.5281/zenodo.1303185},
year = {2018},
date = {2018-09-18},
urldate = {2018-09-18},
booktitle = {Actas de las XXIX Jornadas de Paralelismo},
pages = {201-207},
publisher = {Actas de las Jornadas SARTECO 2018},
abstract = {Para el alumnado de Ingeniería Informática resulta de gran interés alcanzar una visión global de los diferentes niveles de abstracción que permiten entender y explotar un sistema informático. Sin embargo, la organización habitual del Grado de Ingeniería Informática en asignaturas tiende hacia la creación de compartimentos estancos, donde se suele trabajar con un único nivel de abstracción, lo cual conlleva a aislar conceptos y especializar plataformas. Con el objetivo de dotar a un conjunto de asignaturas de una mayor transversalidad, este artículo describe un proyecto consistente en un trazador de rayos paralelo que permite al alumnado experimentar las propiedades de la atomicidad, consistencia, paralelismo y concurrencia de un sistema informático desde el nivel algorítmico de una aplicación hasta las instrucciones de código máquina, incluyendo la interacción entre los diferentes niveles de abstracción del sistema y la relación con las asignaturas involucradas. El desarrollo del proyecto se sustenta con la elaboración de diferentes enunciados de prácticas atendiendo a los distintos niveles de abstracción. Finalmente, se describen los requisitos hardware y software necesarios para el desempeño de las prácticas así como la justificación de la elección del dispositivo Raspberry Pi como plataforma única de desarrollo.},
keywords = {},
pubstate = {published},
tppubtype = {proceedings}
}