Senior Lecturer
Email: briz@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
José Luis Briz is a tenured Associate Professor in the Department of Computer and Systems Engineering at the UZ. His research interests include memory hierarchy and processor microarchitecture, and is currently involved in thermal-aware real-time scheduling on MPSoCs. He does also collaborate in embedded systems projects with the industry. Briz has a combined BS/MS degree in Geology, a MS degree in Computer Science, and a PhD in Computer Engineering, all of them from UZ, having published some contributions to the application of computing to Structural Geology. He is a member of the gaZ group, the I3A Research Institute, and Affiliate of the HiPEAC European Network of Excellence. He is also a member of the ISOC and of the Spanish Society of Computer Architecture (SARTECO)
PUBLICATIONS
2019
Artículos de revista
Desirena-López, G; Ramírez-Treviño, A; Briz, JL; Vázquez, CR; Gómez-Gutiérrez, D
Thermal-aware real-time scheduling using timed continuous petri nets Artículo de revista
En: ACM Transactions on Embedded Computing Systems (TECS), vol. 18, no 4, pp. 1–24, 2019.
@article{desirena2019thermal,
title = {Thermal-aware real-time scheduling using timed continuous petri nets},
author = {G Desirena-López and A Ramírez-Treviño and JL Briz and CR Vázquez and D Gómez-Gutiérrez},
year = {2019},
date = {2019-01-01},
journal = {ACM Transactions on Embedded Computing Systems (TECS)},
volume = {18},
number = {4},
pages = {1--24},
publisher = {ACM New York, NY, USA},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Rubio-Anguiano, L; Desirena-López, G; Ramírez-Treviño, A; Briz, JL
Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN Artículo de revista
En: Discrete Event Dynamic Systems, vol. 29, no 3, pp. 237–264, 2019.
@article{rubio2019energy,
title = {Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN},
author = {L Rubio-Anguiano and G Desirena-López and A Ramírez-Treviño and JL Briz},
year = {2019},
date = {2019-01-01},
journal = {Discrete Event Dynamic Systems},
volume = {29},
number = {3},
pages = {237--264},
publisher = {Springer US},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Miscelánea
Desirena, G; Rubio, L; Ramirez, A; Briz, JL
Thermal-aware hrt scheduling simulation framework Miscelánea
2019.
@misc{desirena2019thermalb,
title = {Thermal-aware hrt scheduling simulation framework},
author = {G Desirena and L Rubio and A Ramirez and JL Briz},
year = {2019},
date = {2019-01-01},
keywords = {},
pubstate = {published},
tppubtype = {misc}
}
Workshops
Valero, Alejandro; Gracia, Darío Suárez; Tejero, Ruben Gran; Ramos, Luis M.; Navarro-Torres, Agustín; Muñoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Murillo, Ana C.; Montijano, Eduardo; Resano, Javier; Villarroya-Gaudó, María; Alastruey-Benedé, Jesús; Torres, Enrique F.; Álvarez, Pedro; Ibáñez, Pablo; Viñals, Víctor
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer Workshop
Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA 2019, Phoenix, AZ, USA, June 22, 2019, ACM, 2019.
@workshop{DBLP:conf/wcae/ValeroGTRNMEBMM19,
title = {Exposing Abstraction-Level Interactions with a Parallel Ray Tracer},
author = {Alejandro Valero and Darío Suárez Gracia and Ruben Gran Tejero and Luis M. Ramos and Agustín Navarro-Torres and Adolfo Muñoz and Joaquín Ezpeleta and José Luis Briz and Ana C. Murillo and Eduardo Montijano and Javier Resano and María Villarroya-Gaudó and Jesús Alastruey-Benedé and Enrique F. Torres and Pedro Álvarez and Pablo Ibáñez and Víctor Viñals},
url = {https://doi.org/10.1145/3338698.3338886},
doi = {10.1145/3338698.3338886},
year = {2019},
date = {2019-01-01},
urldate = {2019-01-01},
booktitle = {Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA
2019, Phoenix, AZ, USA, June 22, 2019},
pages = {5:1--5:8},
publisher = {ACM},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
2018
Artículos de revista
Possignolo, Rafael Trapani; Ebrahimi, Elnaz; Ardestani, Ehsan Khish; Sankaranarayanan, Alamelu; Briz, Jose Luis; Renau, Jose
Gpu ntc process variation compensation with voltage stacking Artículo de revista
En: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no 9, pp. 1713–1726, 2018.
@article{possignolo2018gpu,
title = {Gpu ntc process variation compensation with voltage stacking},
author = {Rafael Trapani Possignolo and Elnaz Ebrahimi and Ehsan Khish Ardestani and Alamelu Sankaranarayanan and Jose Luis Briz and Jose Renau},
year = {2018},
date = {2018-01-01},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume = {26},
number = {9},
pages = {1713--1726},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}