Senior Lecturer
Email: imarin@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
—
PUBLICATIONS
2003
Journal Articles
Torres, Enrique F; Ibanez, Pablo; Vinals, Victor; Llaberia, Jose Maria
Topic 8-Parallel Computer Architecture and Instruction-Level Parallelism-Counteracting Bank Misprediction in Sliced First-Level Caches Journal Article
In: Lecture Notes in Computer Science, vol. 2790, pp. 586–596, 2003.
@article{torres2003topic,
title = {Topic 8-Parallel Computer Architecture and Instruction-Level Parallelism-Counteracting Bank Misprediction in Sliced First-Level Caches},
author = {Enrique F Torres and Pablo Ibanez and Victor Vinals and Jose Maria Llaberia},
year = {2003},
date = {2003-01-01},
journal = {Lecture Notes in Computer Science},
volume = {2790},
pages = {586--596},
publisher = {Berlin: Springer-Verlag, 1973-},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Torres, Enrique F; Ibañez, Pablo; Viñals, Victor; Llabería, Jose Maria
Counteracting bank misprediction in sliced first-level caches Proceedings Article
In: European Conference on Parallel Processing, pp. 586–596, Springer 2003.
@inproceedings{torres2003counteracting,
title = {Counteracting bank misprediction in sliced first-level caches},
author = {Enrique F Torres and Pablo Ibañez and Victor Viñals and Jose Maria Llabería},
year = {2003},
date = {2003-01-01},
booktitle = {European Conference on Parallel Processing},
pages = {586--596},
organization = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2002
Proceedings Articles
Ibáñez, Pablo; Benedé, Jesús Alastruey; Cruz, Oscar Blasco; Yufera, Víctor Viñals; Velasco, José Luis Briz
SPEC CPUy caches en chip: evolución e interacción Proceedings Article
In: XIII Jornadas de Paralelismo: Lleida, 9, 10 y 11 de septiembre de 2002: actas, pp. 19–24, Universitat de Lleida 2002.
@inproceedings{ibanez2002spec,
title = {SPEC CPUy caches en chip: evolución e interacción},
author = {Pablo Ibáñez and Jesús Alastruey Benedé and Oscar Blasco Cruz and Víctor Viñals Yufera and José Luis Briz Velasco},
year = {2002},
date = {2002-01-01},
booktitle = {XIII Jornadas de Paralelismo: Lleida, 9, 10 y 11 de septiembre de 2002: actas},
pages = {19--24},
organization = {Universitat de Lleida},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2001
Proceedings Articles
Garzaran, María Jesús; Brit, JL; Ibáñez, Pablo E; Vinals, Víctor
Hardware prefetching in bus-based multiprocessors: pattern characterization and cost-effective hardware Proceedings Article
In: Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing, pp. 345–354, IEEE 2001.
@inproceedings{garzaran2001hardware,
title = {Hardware prefetching in bus-based multiprocessors: pattern characterization and cost-effective hardware},
author = {María Jesús Garzaran and JL Brit and Pablo E Ibáñez and Víctor Vinals},
year = {2001},
date = {2001-01-01},
booktitle = {Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing},
pages = {345--354},
organization = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Viñals, V; Briz, JL; Ibáñez, PE; Garzarán, MJ
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware Proceedings Article
In: Ninth Euromicro Workshop on Parallel and Distributed Processing (PDP’01), pp. 345–345, 2001.
@inproceedings{vinals2001hardware,
title = {Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware},
author = {V Viñals and JL Briz and PE Ibáñez and MJ Garzarán},
year = {2001},
date = {2001-01-01},
booktitle = {Ninth Euromicro Workshop on Parallel and Distributed Processing (PDP'01)},
pages = {345--345},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}