Senior Lecturer
Email: rgran@unizar.es
Address: Campus Río Ebro, University of Zaragoza
C/María de Luna 1, Ada Byron Building,
50018, Zaragoza, Spain
ABOUT ME
Rubén Gran Tejero graduated in Computer Science from the University of Zaragoza, Spain. He received his Ph.D. from the Polytechnic University of Catalonia (UPC), Spain, in 2010. Since 2010, he has been an Associate Professor at the Department of Computer Science and Systems Engineering, University of Zaragoza. His research interests include hard real-time systems, hardware for reducing worst-case execution time and energy consumption, efficient processor microarchitecture, and effective programming for parallel and heterogeneous systems. Dr. Gran Tejero is member of the Aragon Institute of Engineering Research (I3A) and the Spanish Society of Computer Architecture (SARTECO).
PUBLICATIONS
2019
Proceedings Articles
Valero, Alejandro; Gracia, Darío Suárez; Tejero, Ruben Gran; Ramos, Luis M.; Navarro-Torres, Agustín; Muñoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Murillo, Ana C.; Montijano, Eduardo; Resano, Javier; Villarroya-Gaudó, María; Alastruey-Benedé, Jesús; Torres, Enrique F.; Álvarez, Pedro; Ibáñez, Pablo; Viñals, Víctor
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer Proceedings Article
In: Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA 2019, Phoenix, AZ, USA, June 22, 2019, pp. 5:1–5:8, ACM, 2019.
@inproceedings{DBLP:conf/wcae/ValeroGTRNMEBMM19,
title = {Exposing Abstraction-Level Interactions with a Parallel Ray Tracer},
author = {Alejandro Valero and Darío Suárez Gracia and Ruben Gran Tejero and Luis M. Ramos and Agustín Navarro-Torres and Adolfo Muñoz and Joaquín Ezpeleta and José Luis Briz and Ana C. Murillo and Eduardo Montijano and Javier Resano and María Villarroya-Gaudó and Jesús Alastruey-Benedé and Enrique F. Torres and Pedro Álvarez and Pablo Ibáñez and Víctor Viñals},
url = {https://doi.org/10.1145/3338698.3338886},
doi = {10.1145/3338698.3338886},
year = {2019},
date = {2019-01-01},
booktitle = {Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA
2019, Phoenix, AZ, USA, June 22, 2019},
pages = {5:1--5:8},
publisher = {ACM},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2018
Journal Articles
Valero, Alejandro; Gracia, Darío Suárez; Gran, Rubén; Munoz, Adolfo; Ezpeleta, Joaquín; Briz, José Luis; Ramos, Luis M; Murillo, Ana C; Montijano, Eduardo; Resano, Javier; others,
Atomicidad, Consistencia, Paralelismo y Concurrencia en un Trazador de Rayos elaborado a lo largo del Grado en Ingeniería Informatica Journal Article
In: Actas de las XXIX Jornadas de Paralelismo, pp. 201–207, 2018.
@article{valero2018atomicidad,
title = {Atomicidad, Consistencia, Paralelismo y Concurrencia en un Trazador de Rayos elaborado a lo largo del Grado en Ingeniería Informatica},
author = {Alejandro Valero and Darío Suárez Gracia and Rubén Gran and Adolfo Munoz and Joaquín Ezpeleta and José Luis Briz and Luis M Ramos and Ana C Murillo and Eduardo Montijano and Javier Resano and others},
year = {2018},
date = {2018-01-01},
journal = {Actas de las XXIX Jornadas de Paralelismo},
pages = {201--207},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Nunez-Yanez, Jose; Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Suarez, Dario; Gran, Ruben
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA Journal Article
In: Journal of Supercomputing, pp. 1–2, 2018.
@article{nunez2018correction,
title = {Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA},
author = {Jose Nunez-Yanez and Sam Amiri and Mohammad Hosseinabady and Andrés Rodríguez and Rafael Asenjo and Angeles Navarro and Dario Suarez and Ruben Gran},
year = {2018},
date = {2018-01-01},
journal = {Journal of Supercomputing},
pages = {1--2},
publisher = {Springer Verlag},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Guzmán, Maria Angélica Dávila; Gran, Rubén; Villarroya-Gaudó, María; Súarez-Gracia, Darío
Planificadores para sistemas heterogéneos formados por CPUs, GPUs y FPGAs Journal Article
In: Jornada de Jóvenes Investigadores del I3A, vol. 6, 2018.
@article{guzman2018planificadores,
title = {Planificadores para sistemas heterogéneos formados por CPUs, GPUs y FPGAs},
author = {Maria Angélica Dávila Guzmán and Rubén Gran and María Villarroya-Gaudó and Darío Súarez-Gracia},
year = {2018},
date = {2018-01-01},
journal = {Jornada de Jóvenes Investigadores del I3A},
volume = {6},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Nunez-Yanez, Jose; Hosseinabady, Mohammad; Amiri, Moslem; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Gran-Tejero, Rubén; Suárez-Gracia, Darío
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems Journal Article
In: arXiv preprint arXiv:1802.03316, 2018.
@article{nunez2018parallelizing,
title = {Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems},
author = {Jose Nunez-Yanez and Mohammad Hosseinabady and Moslem Amiri and Andrés Rodríguez and Rafael Asenjo and Angeles Navarro and Rubén Gran-Tejero and Darío Suárez-Gracia},
year = {2018},
date = {2018-01-01},
journal = {arXiv preprint arXiv:1802.03316},
keywords = {},
pubstate = {published},
tppubtype = {article}
}