Teresa Monreal Arnal
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)
Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).
Near-optimal replacement policies for shared caches in multicore processors Journal Article
In: The Journal of Supercomputing, pp. 1–30, 2021.
A fault-tolerant last level cache for CMPs operating at ultra-low voltage Journal Article
In: Journal of Parallel and Distributed Computing, 125 , pp. 31–44, 2019.
ReD: A reuse detector for content selection in exclusive shared last-level caches Journal Article
In: Journal of Parallel and Distributed Computing, 125 , pp. 106–120, 2019.
STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption Inproceedings
In: ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts, pp. 231–234, European Network of Excellence on High Performance and Embedded Architecture~… 2019.
Reuse detector: Improving the management of stt-ram sllcs Journal Article
In: The Computer Journal, 61 (6), pp. 856–880, 2017.