Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain

Contact Information


Teresa Monreal Arnal

Senior Lecturer

Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)


Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).


42 entries « 1 of 9 »


Journal Articles

Díaz, Javier; Ibáñez, Pablo; Monreal, Teresa; Viñals, Víctor; Llabería, José M

Near-optimal replacement policies for shared caches in multicore processors Journal Article

In: The Journal of Supercomputing, pp. 1–30, 2021.



Journal Articles

Ferrerón, Alexandra; Alastruey-Benedé, Jesús; Gracia, Darío Suárez; Arnal, Teresa Monreal; Marín, Pablo Ibáñez; Yúfera, Víctor Viñals

A fault-tolerant last level cache for CMPs operating at ultra-low voltage Journal Article

In: Journal of Parallel and Distributed Computing, vol. 125, pp. 31–44, 2019.


Díaz, Javier; Monreal, Teresa; Ibáñez, Pablo; Llabería, José M; Viñals, Víctor

ReD: A reuse detector for content selection in exclusive shared last-level caches Journal Article

In: Journal of Parallel and Distributed Computing, vol. 125, pp. 106–120, 2019.



Blasco, Carlos Escuín; Arnal, Teresa Monreal; Griñó, José M Llaberia; Yúfera, Victor Viñals; Marín, Pablo Ibáñez

STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption Inproceedings

In: ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts, pp. 231–234, European Network of Excellence on High Performance and Embedded Architecture~… 2019.



Journal Articles

Rodríguez-Rodríguez, Roberto; Díaz, Javier; Castro, Fernando; Ibáñez, Pablo; Chaver, Daniel; Viñals, Víctor; Saez, Juan Carlos; Prieto-Matías, Manuel; Piñuel, Luis; Monreal, T; others,

Reuse detector: Improving the management of stt-ram sllcs Journal Article

In: The Computer Journal, vol. 61, no. 6, pp. 856–880, 2017.


42 entries « 1 of 9 »
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