2026
Proceedings Articles
Siracusa, Marco; Hsu, Olivia; Soria-Pardos, Victor; Randall, Joshua; Grasset, Arnaud; Biscondi, Eric; Joseph, Doug; Allen, Randy; Kjolstad, Fredrik; Planas, Miquel Moretó; Armejach, Adrià
Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures Proceedings Article
In: 2026.
@inproceedings{siracusa2025ember,
title = {Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures},
author = {Marco Siracusa and Olivia Hsu and Victor Soria-Pardos and Joshua Randall and Arnaud Grasset and Eric Biscondi and Doug Joseph and Randy Allen and Fredrik Kjolstad and Miquel Moretó Planas and Adrià Armejach},
url = {https://arxiv.org/pdf/2504.09870},
year = {2026},
date = {2026-01-01},
urldate = {2026-01-01},
journal = {Proceedings of the 22nd ACM International Symposium on Code Generation and Optimization, CGO },
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
2025
Journal Articles
Valero, Alejandro; Lorente, Vicente; Petit, Salvador; Sahuquillo, Julio
Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches Journal Article
In: IEEE Transactions on Computers, vol. 74, no. 8, pp. 2812-2826, 2025, ISSN: 0018-9340.
@article{Valero2025,
title = {Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches},
author = {Alejandro Valero and Vicente Lorente and Salvador Petit and Julio Sahuquillo},
url = {https://www.computer.org/csdl/journal/tc/2025/08/11022726/27fzlt4rw88},
doi = {10.1109/TC.2025.3575909},
issn = {0018-9340},
year = {2025},
date = {2025-08-01},
urldate = {2025-08-01},
journal = {IEEE Transactions on Computers},
volume = {74},
number = {8},
pages = {2812-2826},
abstract = {Static Random-Access Memory (SRAM) is the fastest memory technology and has been the common design choice for implementing first-level (L1) caches in the processor pipeline, where speed is a key design issue that must be fulfilled. On the contrary, this technology offers much lower density compared to other technologies like Dynamic RAM, limiting L1 cache sizes of modern processors to a few tens of KB. This paper explores the use of slower but denser Domain Wall Memory (DWM) technology for L1 caches. This technology provides slow access times since it arranges multiple bits sequentially in a magnetic racetrack. To access these bits, they need to be shifted in order to place them under a header. A 1-bit shift usually takes one processor cycle, which can significantly hurt the application performance, making this working behavior inappropriate for L1 caches. Based on the locality (temporal and spatial) principles exploited by caches, this work proposes the Dual Fast-Track Cache (Dual FTC) design, a new approach to organizing a set of racetracks to build set-associative caches. Compared to a conventional SRAM cache, Dual FTC enhances storage capacity by 5× while incurring minimal shifting overhead, thereby rendering it a practical and appealing solution for L1 cache implementations. Experimental results show that the devised cache organization is as fast as an SRAM cache for 78% and 86% of the L1 data cache hits and L1 instruction cache hits, respectively (i.e., no shift is required). Consequently, due to the larger L1 cache capacities, significant system performance gains (by 22% on average) are obtained under the same silicon area.},
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pubstate = {published},
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Static Random-Access Memory (SRAM) is the fastest memory technology and has been the common design choice for implementing first-level (L1) caches in the processor pipeline, where speed is a key design issue that must be fulfilled. On the contrary, this technology offers much lower density compared to other technologies like Dynamic RAM, limiting L1 cache sizes of modern processors to a few tens of KB. This paper explores the use of slower but denser Domain Wall Memory (DWM) technology for L1 caches. This technology provides slow access times since it arranges multiple bits sequentially in a magnetic racetrack. To access these bits, they need to be shifted in order to place them under a header. A 1-bit shift usually takes one processor cycle, which can significantly hurt the application performance, making this working behavior inappropriate for L1 caches. Based on the locality (temporal and spatial) principles exploited by caches, this work proposes the Dual Fast-Track Cache (Dual FTC) design, a new approach to organizing a set of racetracks to build set-associative caches. Compared to a conventional SRAM cache, Dual FTC enhances storage capacity by 5× while incurring minimal shifting overhead, thereby rendering it a practical and appealing solution for L1 cache implementations. Experimental results show that the devised cache organization is as fast as an SRAM cache for 78% and 86% of the L1 data cache hits and L1 instruction cache hits, respectively (i.e., no shift is required). Consequently, due to the larger L1 cache capacities, significant system performance gains (by 22% on average) are obtained under the same silicon area.
Navarro-Torres, Agustín; Panda, Biswabandan; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Viñnals-Yúfera, Víctor; Ros, Alberto
A Complexity-Effective Local Delta Prefetcher Journal Article
In: IEEE Transactions on Computers, 2025.
@article{navarro2025complexity,
title = {A Complexity-Effective Local Delta Prefetcher},
author = {Agustín Navarro-Torres and Biswabandan Panda and Jesús Alastruey-Benedé and Pablo Ibáñez and Víctor Viñnals-Yúfera and Alberto Ros},
year = {2025},
date = {2025-01-01},
journal = {IEEE Transactions on Computers},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
López-Villellas, Lorién; Mikkelsen, Carl Christian Kjelgaard; Galano-Frutos, Juan José; Marco-Sola, Santiago; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Echenique, Pablo; Moretó, Miquel; Rosa, Maria Cristina De; García-Risueño, Pablo
ILVES: Accurate and Efficient Bond Length and Angle Constraints in Molecular Dynamics Journal Article
In: Journal of Chemical Theory and Computation, vol. 21, no. 18, pp. 8711–8719, 2025.
@article{lopez2025ilves,
title = {ILVES: Accurate and Efficient Bond Length and Angle Constraints in Molecular Dynamics},
author = {Lorién López-Villellas and Carl Christian Kjelgaard Mikkelsen and Juan José Galano-Frutos and Santiago Marco-Sola and Jesús Alastruey-Benedé and Pablo Ibáñez and Pablo Echenique and Miquel Moretó and Maria Cristina De Rosa and Pablo García-Risueño},
year = {2025},
date = {2025-01-01},
journal = {Journal of Chemical Theory and Computation},
volume = {21},
number = {18},
pages = {8711–8719},
publisher = {American Chemical Society},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Pedrajas, Samuel Pérez; Resano, Javier; Gracia, Darío Suárez
BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores Journal Article
In: IEEE Transactions on Circuits and Systems for Artificial Intelligence, pp. 1-12, 2025, ISSN: 2996-6647.
@article{11216142,
title = {BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores},
author = {Samuel Pérez Pedrajas and Javier Resano and Darío Suárez Gracia},
doi = {10.1109/TCASAI.2025.3625517},
issn = {2996-6647},
year = {2025},
date = {2025-01-01},
journal = {IEEE Transactions on Circuits and Systems for Artificial Intelligence},
pages = {1-12},
abstract = {Bayesian Neural Networks (BNN) allow prediction uncertainty estimation, making them a more suitable option for safety-critical applications. However, in BNNs, the forward-pass computational cost is significantly higher than in traditional neural networks (NN), due to the overhead generated by weight sampling. This limits their deployment in edge systems. This paper presents an optimization that allows using lower-cost Uniform distribution sampling instead of Gaussian sampling during BNN inference. Building upon this optimization, this paper proposes a lightweight RISC-V instruction set architecture extension that accelerates BNN inference by introducing fixed point arithmetic operations and an efficient Uniform random number generator. The flexibility of RISC-V enables such domain-specific acceleration, narrowing the performance gap between NNs and BNNs for edge machine learning workloads. The proposed software and hardware optimizations achieve an average speedup of 8.93× while reducing energy consumption per forward pass by 87.12%, increasing image/J efficiency by 8.19×. They have been designed to maintain accuracy, calibration, and uncertainty quality, while optimizing execution efficiency. This has been verified with an extensive validation process that considers relevant model architectures. Additionally, our results highlight that weight sampling is no longer the BNN inference performance bottleneck, shifting the primary limiting factor to control overhead.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Bayesian Neural Networks (BNN) allow prediction uncertainty estimation, making them a more suitable option for safety-critical applications. However, in BNNs, the forward-pass computational cost is significantly higher than in traditional neural networks (NN), due to the overhead generated by weight sampling. This limits their deployment in edge systems. This paper presents an optimization that allows using lower-cost Uniform distribution sampling instead of Gaussian sampling during BNN inference. Building upon this optimization, this paper proposes a lightweight RISC-V instruction set architecture extension that accelerates BNN inference by introducing fixed point arithmetic operations and an efficient Uniform random number generator. The flexibility of RISC-V enables such domain-specific acceleration, narrowing the performance gap between NNs and BNNs for edge machine learning workloads. The proposed software and hardware optimizations achieve an average speedup of 8.93× while reducing energy consumption per forward pass by 87.12%, increasing image/J efficiency by 8.19×. They have been designed to maintain accuracy, calibration, and uncertainty quality, while optimizing execution efficiency. This has been verified with an extensive validation process that considers relevant model architectures. Additionally, our results highlight that weight sampling is no longer the BNN inference performance bottleneck, shifting the primary limiting factor to control overhead.
Bazo, Antonio; López-Villellas, Lorién; Mataloni, Matilde; Bolea-Fernandez, Eduardo; Rua-Ibarz, Ana; Grotti, Marco; Aramendía, Maite; Resano, Martín
Improving detection and figures of merit in single-particle inductively coupled plasma-mass spectrometry via transient event heights Journal Article
In: Analytica Chimica Acta, pp. 344694, 2025.
@article{bazo2025improving,
title = {Improving detection and figures of merit in single-particle inductively coupled plasma-mass spectrometry via transient event heights},
author = {Antonio Bazo and Lorién López-Villellas and Matilde Mataloni and Eduardo Bolea-Fernandez and Ana Rua-Ibarz and Marco Grotti and Maite Aramendía and Martín Resano},
year = {2025},
date = {2025-01-01},
journal = {Analytica Chimica Acta},
pages = {344694},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
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López-Villellas, Lorién; Iñiguez, Cristian; Jiménez-Blanco, Albert; Aguado-Puig, Quim; Moretó, Miquel; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Marco-Sola, Santiago
Singletrack: An Algorithm for Improving Memory Consumption and Performance of Gap-Affine Sequence Alignment Journal Article
In: bioRxiv, pp. 2025–10, 2025.
@article{lopez2025singletrack,
title = {Singletrack: An Algorithm for Improving Memory Consumption and Performance of Gap-Affine Sequence Alignment},
author = {Lorién López-Villellas and Cristian Iñiguez and Albert Jiménez-Blanco and Quim Aguado-Puig and Miquel Moretó and Jesús Alastruey-Benedé and Pablo Ibáñez and Santiago Marco-Sola},
year = {2025},
date = {2025-01-01},
journal = {bioRxiv},
pages = {2025–10},
publisher = {Cold Spring Harbor Laboratory},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Mikkelsen, Carl Christian Kjelgaard; López-Villellas, Lorién
How Accurate is Richardson’s Error Estimate? Journal Article
In: Concurrency and Computation: Practice and Experience, vol. 37, no. 27-28, pp. e70305, 2025.
@article{kjelgaard2025accurate,
title = {How Accurate is Richardson's Error Estimate?},
author = {Carl Christian Kjelgaard Mikkelsen and Lorién López-Villellas},
year = {2025},
date = {2025-01-01},
journal = {Concurrency and Computation: Practice and Experience},
volume = {37},
number = {27-28},
pages = {e70305},
publisher = {John Wiley & Sons, Inc. Hoboken, USA},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Soria-Pardos, Víctor; Armejach, Adrià; Mück, Tiago; Gracia, Darío Suárez; Joao, Jose; Moretó, Miquel
Delegato: Locality-Aware Atomic Memory Operations on Chiplets Proceedings Article
In: Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, pp. 1793–1808, ACM, 2025.
@inproceedings{soria2025delegato,
title = {Delegato: Locality-Aware Atomic Memory Operations on Chiplets},
author = {Víctor Soria-Pardos and Adrià Armejach and Tiago Mück and Darío Suárez Gracia and Jose Joao and Miquel Moretó},
url = {https://dl.acm.org/doi/full/10.1145/3725843.3756030},
doi = {10.1145/3725843.375603},
year = {2025},
date = {2025-01-01},
urldate = {2025-01-01},
booktitle = {Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture},
pages = {1793–1808},
publisher = {ACM},
abstract = {The irruption of chiplet-based architectures has been a game changer, enabling higher transistor integration and core counts in a single socket. However, chiplets impose higher and non-uniform memory access (NUMA) latencies than monolithic integration. This harms the efficiency of atomic memory operations (AMOs), which are fundamental to implementing fine-grained synchronization and concurrent data structures on large systems. AMOs are executed either near the core (near) or at a remote location within the cache hierarchy (far). On near AMOs, the core’s private cache fetches the target cache line in exclusiveness to modify it locally. Near AMOs cause significant data movement between private caches, especially harming parallel applications’ performance on chiplet-based architectures. Alternatively, far AMOs can alleviate the communication overhead by reducing data movement between processing elements. However, current multicore architectures only support one type of far AMO, which sends all updates to a single serialization point (centralized AMOs).
This work introduces two new types of far AMOs, delegated and migrating, that execute AMOs remotely without centralizing updates in a single point of the cache hierarchy. Combining centralized, delegated, and migrating AMOs allows the directory to select the best location to execute AMOs. Moreover, we propose Delegato, a tracing optimization to effectively transport usage information from private caches to the directory to predict the best atomic type to issue accurately. Additionally, we design a simple predictor on top of Delegato that seamlessly selects the best placement to perform AMOs based on the data access pattern and usage activity of cores. Our evaluation using gem5 shows that Delegato can speed up applications on average by 1.07 × over centralized AMOs and by 1.13 × over the state-of-the-art AMO predictor.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The irruption of chiplet-based architectures has been a game changer, enabling higher transistor integration and core counts in a single socket. However, chiplets impose higher and non-uniform memory access (NUMA) latencies than monolithic integration. This harms the efficiency of atomic memory operations (AMOs), which are fundamental to implementing fine-grained synchronization and concurrent data structures on large systems. AMOs are executed either near the core (near) or at a remote location within the cache hierarchy (far). On near AMOs, the core’s private cache fetches the target cache line in exclusiveness to modify it locally. Near AMOs cause significant data movement between private caches, especially harming parallel applications’ performance on chiplet-based architectures. Alternatively, far AMOs can alleviate the communication overhead by reducing data movement between processing elements. However, current multicore architectures only support one type of far AMO, which sends all updates to a single serialization point (centralized AMOs).
This work introduces two new types of far AMOs, delegated and migrating, that execute AMOs remotely without centralizing updates in a single point of the cache hierarchy. Combining centralized, delegated, and migrating AMOs allows the directory to select the best location to execute AMOs. Moreover, we propose Delegato, a tracing optimization to effectively transport usage information from private caches to the directory to predict the best atomic type to issue accurately. Additionally, we design a simple predictor on top of Delegato that seamlessly selects the best placement to perform AMOs based on the data access pattern and usage activity of cores. Our evaluation using gem5 shows that Delegato can speed up applications on average by 1.07 × over centralized AMOs and by 1.13 × over the state-of-the-art AMO predictor.
This work introduces two new types of far AMOs, delegated and migrating, that execute AMOs remotely without centralizing updates in a single point of the cache hierarchy. Combining centralized, delegated, and migrating AMOs allows the directory to select the best location to execute AMOs. Moreover, we propose Delegato, a tracing optimization to effectively transport usage information from private caches to the directory to predict the best atomic type to issue accurately. Additionally, we design a simple predictor on top of Delegato that seamlessly selects the best placement to perform AMOs based on the data access pattern and usage activity of cores. Our evaluation using gem5 shows that Delegato can speed up applications on average by 1.07 × over centralized AMOs and by 1.13 × over the state-of-the-art AMO predictor.
Soria-Pardos, Víctor; Armejach, Adrià; Suárez, Darío; Martinot, Didier; Grasset, Arnaud; Moretó, Miquel
FLAMA: Architecting floating-point atomic memory operations for heterogeneous HPC systems Proceedings Article
In: 2025 28th Euromicro Conference on Digital System Design (DSD), pp. 435–442, IEEE IEEE, 2025.
@inproceedings{soria2025flama,
title = {FLAMA: Architecting floating-point atomic memory operations for heterogeneous HPC systems},
author = {Víctor Soria-Pardos and Adrià Armejach and Darío Suárez and Didier Martinot and Arnaud Grasset and Miquel Moretó},
url = {https://upcommons.upc.edu/server/api/core/bitstreams/9199c411-ce89-4327-a06b-bf21838aa8db/content},
doi = {10.1109/DSD67783.2025.00066},
year = {2025},
date = {2025-01-01},
urldate = {2025-01-01},
booktitle = {2025 28th Euromicro Conference on Digital System Design (DSD)},
pages = {435–442},
publisher = {IEEE},
organization = {IEEE},
abstract = {Current heterogeneous systems integrate generalpurpose Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs). The efficient use of such systems requires a significant programming effort to distribute computation and synchronize across devices, which usually involves using Atomic Memory Operations (AMOs). Arm recently launched a floating-point Atomic Memory Operations (FAMOs) extension to perform atomic updates on floating-point data types specifically. This work characterizes and models heterogeneous architectures to understand how floating-point AMOs impact graph, Machine Learning (ML), and high-performance computing (HPC) workloads. Our analysis shows that many AMOs are performed on floating-point data, which modern systems execute using inefficient compare-and-swap (CAS) constructs. Therefore, replacing CASbased constructs with FAMOs can improve a wide range of workloads. Moreover, we analyze the trade-offs of executing FAMOs at different memory hierarchy levels, either in private caches (near) or remotely in shared caches (far). We have extended the widely used AMBA CHI protocol to evaluate such FAMO support on a simulated chiplet-based heterogeneous architecture. While near FAMOs achieve an average 1.34× speed-up, far FAMOs reach an average 1.58× speed-up. We conclude that FAMOs can bridge the gap between CPU architecture and accelerators and enabling synchronization in key application domains.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Current heterogeneous systems integrate generalpurpose Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs). The efficient use of such systems requires a significant programming effort to distribute computation and synchronize across devices, which usually involves using Atomic Memory Operations (AMOs). Arm recently launched a floating-point Atomic Memory Operations (FAMOs) extension to perform atomic updates on floating-point data types specifically. This work characterizes and models heterogeneous architectures to understand how floating-point AMOs impact graph, Machine Learning (ML), and high-performance computing (HPC) workloads. Our analysis shows that many AMOs are performed on floating-point data, which modern systems execute using inefficient compare-and-swap (CAS) constructs. Therefore, replacing CASbased constructs with FAMOs can improve a wide range of workloads. Moreover, we analyze the trade-offs of executing FAMOs at different memory hierarchy levels, either in private caches (near) or remotely in shared caches (far). We have extended the widely used AMBA CHI protocol to evaluate such FAMO support on a simulated chiplet-based heterogeneous architecture. While near FAMOs achieve an average 1.34× speed-up, far FAMOs reach an average 1.58× speed-up. We conclude that FAMOs can bridge the gap between CPU architecture and accelerators and enabling synchronization in key application domains.
2024
Journal Articles
Toca-Díaz, Yamilka; Tejero, Rubén Gran; Valero, Alejandro
Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators Journal Article
In: Journal of Systems Architecture, vol. 157, pp. 1-13, 2024, ISSN: 1383-7621.
@article{Toca-Díaz2024,
title = {Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators},
author = {Yamilka Toca-Díaz and Rubén Gran Tejero and Alejandro Valero},
url = {https://www.sciencedirect.com/science/article/pii/S1383762124002297},
doi = {https://doi.org/10.1016/j.sysarc.2024.103292},
issn = {1383-7621},
year = {2024},
date = {2024-12-01},
urldate = {2024-12-01},
journal = {Journal of Systems Architecture},
volume = {157},
pages = {1-13},
abstract = {Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low Vdd voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at Vmin, respectively.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low Vdd voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at Vmin, respectively.
Toca-Díaz, Yamilka; Palacios, Reynier Hernández; Tejero, Ruben Gran; Valero, Alejandro
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage Journal Article
In: Microprocessors and Microsystems, vol. 106, pp. 1-13, 2024, ISSN: 0141-9331.
@article{Toca-Díaz2024b,
title = {Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage},
author = {Yamilka Toca-Díaz and Reynier Hernández Palacios and Ruben Gran Tejero and Alejandro Valero},
url = {https://www.sciencedirect.com/science/article/pii/S0141933124000188},
doi = {https://doi.org/10.1016/j.micpro.2024.105023},
issn = {0141-9331},
year = {2024},
date = {2024-04-01},
urldate = {2024-04-01},
journal = {Microprocessors and Microsystems},
volume = {106},
pages = {1-13},
abstract = {Aggressively reducing the supply voltage (Vdd) below the safe threshold voltage (Vmin) can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes. This work addresses the impact of permanent faults on the accuracy of a Convolutional Neural Network (CNN) inference accelerator using on-chip activation memories supplied at low Vdd below Vmin. Based on a characterization study of fault patterns, this paper proposes two low-cost microarchitectural techniques, namely Flip-and-Patch, which maintain the original accuracy of CNN applications even in the presence of a high number of faults caused by operating at Vdd < Vmin. Unlike existing techniques, Flip-and-Patch remains transparent to the programmer and does not rely on application characteristics, making it easily applicable to real CNN accelerators.
Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Aggressively reducing the supply voltage (Vdd) below the safe threshold voltage (Vmin) can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes. This work addresses the impact of permanent faults on the accuracy of a Convolutional Neural Network (CNN) inference accelerator using on-chip activation memories supplied at low Vdd below Vmin. Based on a characterization study of fault patterns, this paper proposes two low-cost microarchitectural techniques, namely Flip-and-Patch, which maintain the original accuracy of CNN applications even in the presence of a high number of faults caused by operating at Vdd < Vmin. Unlike existing techniques, Flip-and-Patch remains transparent to the programmer and does not rely on application characteristics, making it easily applicable to real CNN accelerators.
Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%.
Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%.
López-Villellas, Lorién; Langarita-Benítez, Rubén; Badouh, Asaf; Soria-Pardos, Víctor; Aguado-Puig, Quim; López-Paradís, Guillem; Doblas, Max; Setoain, Javier; Kim, Chulho; Ono, Makoto; Armejach, Adrià; Marco-Sola, Santiago; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Moretó, Miquel
GenArchBench: A genomics benchmark suite for arm HPC processors Journal Article
In: Future Generation Computer Systems, vol. 157, pp. 313-329, 2024, ISSN: 0167-739X.
@article{LOPEZVILLELLAS2024313,
title = {GenArchBench: A genomics benchmark suite for arm HPC processors},
author = {Lorién López-Villellas and Rubén Langarita-Benítez and Asaf Badouh and Víctor Soria-Pardos and Quim Aguado-Puig and Guillem López-Paradís and Max Doblas and Javier Setoain and Chulho Kim and Makoto Ono and Adrià Armejach and Santiago Marco-Sola and Jesús Alastruey-Benedé and Pablo Ibáñez and Miquel Moretó},
url = {https://www.sciencedirect.com/science/article/pii/S0167739X24001250},
doi = {https://doi.org/10.1016/j.future.2024.03.050},
issn = {0167-739X},
year = {2024},
date = {2024-01-01},
journal = {Future Generation Computer Systems},
volume = {157},
pages = {313-329},
abstract = {Arm usage has substantially grown in the High-Performance Computing (HPC) community. Japanese supercomputer Fugaku, powered by Arm-based A64FX processors, held the top position on the Top500 list between June 2020 and June 2022, currently sitting in the fourth position. The recently released 7th generation of Amazon EC2 instances for compute-intensive workloads (C7 g) is also powered by Arm Graviton3 processors. Projects like European Mont-Blanc and U.S. DOE/NNSA Astra are further examples of Arm irruption in HPC. In parallel, over the last decade, the rapid improvement of genomic sequencing technologies and the exponential growth of sequencing data has placed a significant bottleneck on the computational side. While most genomics applications have been thoroughly tested and optimized for x86 systems, just a few are prepared to perform efficiently on Arm machines. Moreover, these applications do not exploit the newly introduced Scalable Vector Extensions (SVE). This paper presents GenArchBench, the first genome analysis benchmark suite targeting Arm architectures. We have selected computationally demanding kernels from the most widely used tools in genome data analysis and ported them to Arm-based A64FX and Graviton3 processors. Overall, the GenArch benchmark suite comprises 13 multi-core kernels from critical stages of widely-used genome analysis pipelines, including base-calling, read mapping, variant calling, and genome assembly. Our benchmark suite includes different input data sets per kernel (small and large), each with a corresponding regression test to verify the correctness of each execution automatically. Moreover, the porting features the usage of the novel Arm SVE instructions, algorithmic and code optimizations, and the exploitation of Arm-optimized libraries. We present the optimizations implemented in each kernel and a detailed performance evaluation and comparison of their performance on four different HPC machines (i.e., A64FX, Graviton3, Intel Xeon Skylake Platinum, and AMD EPYC Rome). Overall, the experimental evaluation shows that Graviton3 outperforms other machines on average. Moreover, we observed that the performance of the A64FX is significantly constrained by its small memory hierarchy and latencies. Additionally, as proof of concept, we study the performance of a production-ready tool that exploits two of the ported and optimized genomic kernels.},
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pubstate = {published},
tppubtype = {article}
}
Arm usage has substantially grown in the High-Performance Computing (HPC) community. Japanese supercomputer Fugaku, powered by Arm-based A64FX processors, held the top position on the Top500 list between June 2020 and June 2022, currently sitting in the fourth position. The recently released 7th generation of Amazon EC2 instances for compute-intensive workloads (C7 g) is also powered by Arm Graviton3 processors. Projects like European Mont-Blanc and U.S. DOE/NNSA Astra are further examples of Arm irruption in HPC. In parallel, over the last decade, the rapid improvement of genomic sequencing technologies and the exponential growth of sequencing data has placed a significant bottleneck on the computational side. While most genomics applications have been thoroughly tested and optimized for x86 systems, just a few are prepared to perform efficiently on Arm machines. Moreover, these applications do not exploit the newly introduced Scalable Vector Extensions (SVE). This paper presents GenArchBench, the first genome analysis benchmark suite targeting Arm architectures. We have selected computationally demanding kernels from the most widely used tools in genome data analysis and ported them to Arm-based A64FX and Graviton3 processors. Overall, the GenArch benchmark suite comprises 13 multi-core kernels from critical stages of widely-used genome analysis pipelines, including base-calling, read mapping, variant calling, and genome assembly. Our benchmark suite includes different input data sets per kernel (small and large), each with a corresponding regression test to verify the correctness of each execution automatically. Moreover, the porting features the usage of the novel Arm SVE instructions, algorithmic and code optimizations, and the exploitation of Arm-optimized libraries. We present the optimizations implemented in each kernel and a detailed performance evaluation and comparison of their performance on four different HPC machines (i.e., A64FX, Graviton3, Intel Xeon Skylake Platinum, and AMD EPYC Rome). Overall, the experimental evaluation shows that Graviton3 outperforms other machines on average. Moreover, we observed that the performance of the A64FX is significantly constrained by its small memory hierarchy and latencies. Additionally, as proof of concept, we study the performance of a production-ready tool that exploits two of the ported and optimized genomic kernels.
Torres-Macías, A. G.; Ramírez-Treviño, A.; Briz, J. L.; Segarra, J.; Blanco-Alcaine, H.
Modeling Time-Sensitive Networking Using Timed Continuous Petri Nets Journal Article
In: IFAC-PapersOnLine, vol. 58, no. 1, pp. 300-305, 2024.
@article{Tor:24a,
title = {Modeling Time-Sensitive Networking Using Timed Continuous Petri Nets},
author = {A. G. Torres-Macías and A. Ramírez-Treviño and J. L. Briz and J. Segarra and H. Blanco-Alcaine},
url = {https://doi.org/10.1016/j.ifacol.2024.07.051},
year = {2024},
date = {2024-01-01},
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Torres-Macías, A. G.; Segarra, J.; Briz, J. L.; Ramírez-Treviño, A.; Blanco-Alcaine, H.
Fast IEEE802.1Qbv Gate Scheduling Through Integer Linear Programming Journal Article
In: IEEE Access, vol. 12, pp. 111239-111250, 2024.
@article{Tor:24b,
title = {Fast IEEE802.1Qbv Gate Scheduling Through Integer Linear Programming},
author = {A. G. Torres-Macías and J. Segarra and J. L. Briz and A. Ramírez-Treviño and H. Blanco-Alcaine},
url = {https://doi.org/10.1109/ACCESS.2024.3440828},
year = {2024},
date = {2024-01-01},
journal = {IEEE Access},
volume = {12},
pages = {111239-111250},
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Mikkelsen, Carl Christian Kjelgaard; López-Villellas, Lorién; García-Risueño, Pablo
Newton’s method revisited: How accurate do we have to be? Journal Article
In: Concurrency and Computation: Practice and Experience, vol. 36, no. 10, pp. e7853, 2024.
@article{kjelgaard2024newton,
title = {Newton's method revisited: How accurate do we have to be?},
author = {Carl Christian Kjelgaard Mikkelsen and Lorién López-Villellas and Pablo García-Risueño},
year = {2024},
date = {2024-01-01},
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Proceedings Articles
Toca-Díaz, Yamilka; Tejero, Rubén Gran; Valero, Alejandro
Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage Proceedings Article
In: pp. 92-95, 2024, ISBN: 979-8-3503-8040-8.
@inproceedings{Toca-Díaz2024c,
title = {Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage},
author = {Yamilka Toca-Díaz and Rubén Gran Tejero and Alejandro Valero},
url = {https://ieeexplore.ieee.org/document/10817950},
doi = {https://doi.org/10.1109/ICCD63220.2024.00024},
isbn = {979-8-3503-8040-8},
year = {2024},
date = {2024-11-18},
urldate = {2024-11-18},
journal = {Proceedings of the 42nd IEEE International Conference on Computer Design (ICCD 2024)},
pages = {92-95},
abstract = {Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) brings significant energy savings in digital CMOS circuits but introduces reliability challenges due to increased risk of bitcell permanent faults. This work explores the impact of such faults on the accuracy of a CNN inference accelerator supplying on-chip activation memories at ultra-low Vdd. By examining fault pat-terns, activation values, and memory usage, this paper proposes two microarchitectural techniques exploiting activation outliers and activation memory underutilization. These approaches are cost-effective, do not require programmer intervention, and are application-independent. Experimental results show that the proposed approaches maintain the original CNN accuracy and achieve energy savings by 2.1 % and 8.2 % compared to the state-of-the-art technique and a conventional accelerator supplied at Vmin, respectively, with a negligible impact on the system performance (less than 0.25 %).},
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Underscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) brings significant energy savings in digital CMOS circuits but introduces reliability challenges due to increased risk of bitcell permanent faults. This work explores the impact of such faults on the accuracy of a CNN inference accelerator supplying on-chip activation memories at ultra-low Vdd. By examining fault pat-terns, activation values, and memory usage, this paper proposes two microarchitectural techniques exploiting activation outliers and activation memory underutilization. These approaches are cost-effective, do not require programmer intervention, and are application-independent. Experimental results show that the proposed approaches maintain the original CNN accuracy and achieve energy savings by 2.1 % and 8.2 % compared to the state-of-the-art technique and a conventional accelerator supplied at Vmin, respectively, with a negligible impact on the system performance (less than 0.25 %).
Pérez, Samuel; Resano, Javier; Gracia, Darío Suárez
Accelerating Bayesian Neural Networks on Low-Power Edge RISC-V Processors Proceedings Article
In: 2024 IEEE 24th International Conference on Nanotechnology (NANO), pp. 507-512, 2024, ISSN: 1944-9380.
@inproceedings{10628877,
title = {Accelerating Bayesian Neural Networks on Low-Power Edge RISC-V Processors},
author = {Samuel Pérez and Javier Resano and Darío Suárez Gracia},
doi = {10.1109/NANO61778.2024.10628877},
issn = {1944-9380},
year = {2024},
date = {2024-07-01},
booktitle = {2024 IEEE 24th International Conference on Nanotechnology (NANO)},
pages = {507-512},
abstract = {Neural Networks (NN s) are a very popular solution for classification tasks. As the combination of Internet of Things (IoT) with Machine Learning (ML), also known as TinyML, grows in popularity, more NN are being executed on low-end edge systems. The reliability of the predictions is crucial for safety-critical applications. Bayesian Neural Networks (BNNs) address this issue by calculating uncertainty metrics with their predictions at the cost of increasing computing requirements. This work addresses the challenges of executing BNNs inference on low-end systems. BNNs require multiple forward passes in which the weights are sampled from distributions. This sampling process can take up to 85,13% of execution time. This work optimizes the weight sampling and integrates it within a low cost custom extension for a RISC- V CPU, improving speedup up to x 8,10 and similar energy savings.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Neural Networks (NN s) are a very popular solution for classification tasks. As the combination of Internet of Things (IoT) with Machine Learning (ML), also known as TinyML, grows in popularity, more NN are being executed on low-end edge systems. The reliability of the predictions is crucial for safety-critical applications. Bayesian Neural Networks (BNNs) address this issue by calculating uncertainty metrics with their predictions at the cost of increasing computing requirements. This work addresses the challenges of executing BNNs inference on low-end systems. BNNs require multiple forward passes in which the weights are sampled from distributions. This sampling process can take up to 85,13% of execution time. This work optimizes the weight sampling and integrates it within a low cost custom extension for a RISC- V CPU, improving speedup up to x 8,10 and similar energy savings.
Mikkelsen, Carl Christian Kjelgaard; López-Villellas, Lorién
The need for accuracy and smoothness in numerical simulations Proceedings Article
In: International Conference on Parallel Processing and Applied Mathematics, pp. 3–16, Springer 2024.
@inproceedings{kjelgaard2024need,
title = {The need for accuracy and smoothness in numerical simulations},
author = {Carl Christian Kjelgaard Mikkelsen and Lorién López-Villellas},
year = {2024},
date = {2024-01-01},
booktitle = {International Conference on Parallel Processing and Applied Mathematics},
pages = {3–16},
organization = {Springer},
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2023
Journal Articles
Mikkelsen, Carl Christian Kjelgaard; López‐Villellas, Lorién; García‐Risueño, Pablo
Newton’s method revisited: How accurate do we have to be? Journal Article
In: Concurrency and Computation: Practice and Experience, vol. 36, no. 10, 2023, ISSN: 1532-0634.
@article{KjelgaardMikkelsen2023,
title = {Newton’s method revisited: How accurate do we have to be?},
author = {Carl Christian Kjelgaard Mikkelsen and Lorién López‐Villellas and Pablo García‐Risueño},
url = {http://dx.doi.org/10.1002/cpe.7853},
doi = {10.1002/cpe.7853},
issn = {1532-0634},
year = {2023},
date = {2023-07-01},
journal = {Concurrency and Computation: Practice and Experience},
volume = {36},
number = {10},
publisher = {Wiley},
keywords = {},
pubstate = {published},
tppubtype = {article}
}