Senior Lecturer
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)
Email: teresa@ac.upc.edu
Address: Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain
ABOUT ME
Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).
PUBLICATIONS
2011
Journal Articles
Gracia, Darío Suárez; Dimitrakopoulos, Giorgos; Arnal, Teresa Monreal; Katevenis, Manolis GH; Yúfera, Víctor Viñals
LP-NUCA: Networks-in-cache for high-performance low-power embedded processors Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 8, pp. 1510–1523, 2011.
@article{gracia2011lp,
title = {LP-NUCA: Networks-in-cache for high-performance low-power embedded processors},
author = {Darío Suárez Gracia and Giorgos Dimitrakopoulos and Teresa Monreal Arnal and Manolis GH Katevenis and Víctor Viñals Yúfera},
year = {2011},
date = {2011-01-01},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume = {20},
number = {8},
pages = {1510--1523},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Gracia, Darío Suárez; Arnal, Teresa Monreal; Yúfera, Víctor Viñals
An adaptive controller to save dynamic energy in lp-nuca Journal Article
In: Proc. of the 22th Jornadas de Paralelismo (JJPAR’11), 2011.
@article{gracia2011adaptive,
title = {An adaptive controller to save dynamic energy in lp-nuca},
author = {Darío Suárez Gracia and Teresa Monreal Arnal and Víctor Viñals Yúfera},
year = {2011},
date = {2011-01-01},
journal = {Proc. of the 22th Jornadas de Paralelismo (JJPAR’11)},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Dimitrakopoulos, G; Katevenis, M; Monreal, T; Suárez, D; Viñals, V
LP-NUCA: networks-in-cache for high-performance low-power embedded processors Journal Article
In: 2011.
@article{dimitrakopoulos2011lp,
title = {LP-NUCA: networks-in-cache for high-performance low-power embedded processors},
author = {G Dimitrakopoulos and M Katevenis and T Monreal and D Suárez and V Viñals},
year = {2011},
date = {2011-01-01},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Suárez, D; Monreal, T; Viñals, V
A comparison of cache hierarchies for SMT processors Journal Article
In: Proc. of the 22nd Jornadas de Paralelismo, 2011.
@article{suarez2011comparison,
title = {A comparison of cache hierarchies for SMT processors},
author = {D Suárez and T Monreal and V Viñals},
year = {2011},
date = {2011-01-01},
journal = {Proc. of the 22nd Jornadas de Paralelismo},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Proceedings Articles
Gracía, Dario Suárez; Arnal, Teresa Monreal; Yúfera, Víctor Viñals
A comparison of cache hierarchies for SMT processors Proceedings Article
In: XXII Jornadas de Paralelismo: La Laguna, 7-9 septiembre 2011: actas, pp. 563–568, Universidad de La Laguna. Servicio de Publicaciones 2011.
@inproceedings{suarez2011comparisonb,
title = {A comparison of cache hierarchies for SMT processors},
author = {Dario Suárez Gracía and Teresa Monreal Arnal and Víctor Viñals Yúfera},
year = {2011},
date = {2011-01-01},
booktitle = {XXII Jornadas de Paralelismo: La Laguna, 7-9 septiembre 2011: actas},
pages = {563--568},
organization = {Universidad de La Laguna. Servicio de Publicaciones},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}