Senior Lecturer
Computer Architecture Department (DAC),
Universitat Politècnica de Catalunya (UPC)

Email: teresa@ac.upc.edu

Address: Campus Diagonal Nord, UPC
Jordi Girona , 1-3,
08034, Barcelona, Spain

ABOUT ME

Teresa Monreal Arnal received the MS degree in Mathematics and the PhD degree in Computer Science from the University of Zaragoza, Spain, in 1991 and 2003, respectively. Until 2007, she was with the Informática e Ingeniería de Sistemas Department (DIIS) at the University of Zaragoza, Spain. Currently, she is an Associate Professor with the Computer Architecture Department (DAC) at the Universitat Politècnica de Catalunya (UPC), Spain. Her research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. She collaborates actively with the Grupo de Arquitectura de Computadores from the University of Zaragoza (gaZ).

PUBLICATIONS
45 entries « 8 of 9 »

1999

Proceedings Articles

Monreal, Teresa; González, Antonio; Valero, Mateo; González, José; Viñals, Victor

Delaying physical register allocation through virtual-physical registers Proceedings Article

In: MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 186–192, IEEE 1999.

BibTeX

Monreal, Teresa; González, Antonio; Valero, Mateo; González, José; Viñals, Victor

Delaying Physical Register Allocation Through Virtual-Physical Registers Proceedings Article

In: Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 186-192, Institute of Electrical & Electronics Engineers (IEEE) IEEE Computer Society, Haifa, Israel, 1999.

BibTeX

1997

Proceedings Articles

González, Antonio; Valero, Mateo; González, José; Monreal, Teresa

Virtual registers Proceedings Article

In: Proceedings Fourth International Conference on High-Performance Computing, pp. 364–369, IEEE 1997.

BibTeX

0000

Journal Articles

Ferrerón, Alexandra; Suárez, Darío; Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor

Low Complexity Improvements for Chip Multiprocessors Shared Caches at Ultra-low Voltages Journal Article

In: 0000.

BibTeX

Alastruey, Jesús; Monreal, Teresa; Viñals, Víctor; Valero, Mateo

Limits on Early Release of Physical Registers Journal Article

In: 0000.

BibTeX

45 entries « 8 of 9 »